- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365988 > TSPC603R TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz PDF資料下載
參數(shù)資料
| 型號： | TSPC603R |
| 英文描述： | TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz |
| 中文描述： | TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫 |
| 文件頁數(shù)： | 3/44頁 |
| 文件大小： | 636K |
| 代理商： | TSPC603R |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
3
TSPC603R
2125A
–
HIREL
–
04/02
Introduction
The 603r is a low-power implementation of the PowerPC microprocessor family of
reduced instruction set computer (RISC) microprocessors. The 603r implements the
32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses,
integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer
data types, 64-bit addressing, and other features required to complete the 64-bit
architecture.
The 603r provides four software controllable power-saving modes. Three of the modes
(the nap, doze, and sleep modes) are static in nature, and progressively reduce the
amount of power dissipated by the processor. The fourth is a dynamic power manage-
ment mode that causes the functional units in the 603r to automatically enter a
low-power mode when the functional units are idle without affecting operational perfor-
mance, software execution, or any external hardware.
The 603r is a superscalar processor capable of issuing and retiring as many as three
instructions per clock. Instructions can execute out of order for increased performance;
however, the 603r makes completion appear sequential.
The 603e integrates five execution units
—
an integer unit (IU), a floating-point unit
(FPU), a branch processing unit (BPU), a load/store unit (LSU) and a system register
unit (SRU). The ability to execute five instructions in parallel and the use of simple
instructions with rapid execution times yield high efficiency and throughput for
603r-based systems. Most integer instructions execute in one clock cycle. The FPU is
pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
The 603r provides independent on-chip, 16-Kbyte, four-way set-associative, physically
addressed caches for instructions and data and on-chip instruction and data memory
management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data
and instruction translation look aside buffers (DTLB and ITLB) that provide support for
demand-paged virtual memory address translation and variable-sized block translation.
The TLBs and caches use a least recently used (LRU) replacement algorithm. The 603r
also supports block address translation through the use of two independent instruction
and data block address translation (IBAT and DBAT) arrays of four entries each. Effec-
tive addresses are compared simultaneously with all four entries in the BAT array during
block translation. In accordance with the PowerPC architecture, if an effective address
hits in both the TLB and BAT array, the BAT translation takes priority.
The 603r has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603r
interface protocol allows multiple masters to compete for system resources through a
central external arbiter. The 603r provides a three-state coherency protocol that sup-
ports the exclusive, modified, and invalid cache states. This protocol as a compatible
subset of the MESI (modified/exclusive/shared/invalid) four-state protocol and operates
coherently in systems that contain four-state caches. The 603r supports single-beat and
burst data transfers for memory accesses, and supports memory-mapped I/O.
The 603r uses an advanced, 0.29 μm 5 metal layer CMOS process technology and
maintains full interface compatibility with TTL devices.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSPC750AMGS10LH | Microprocessor |
| TSPC750AMGS12LE | Microprocessor |
| TSPC750AMGSU10LE | Microprocessor |
| TSPC750AMGSU10LH | Microprocessor |
| TSPC750AMGSU12LE | Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMG10LC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。