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| 型號(hào)： | TSPC603R |
| 英文描述： | TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz |
| 中文描述： | TSPC603R [更新4 / 02。 44頁(yè)] 32位RISC微處理器。 166-300兆赫 |
| 文件頁(yè)數(shù)： | 19/44頁(yè) |
| 文件大小： | 636K |
| 代理商： | TSPC603R |
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19
TSPC603R
2125A
–
HIREL
–
04/02
Figure 7.
Mode Select Input Timing Diagram
Output AC Specifications
Table 13 provides the output AC timing specifications for the 603r (shown in Figure 8).
Notes:
1. All output specifications are measured from the 1.4V of the rising edge of SYSCLK to the TTL level (0.8V or 2.0V) of the sig-
nal in question. Both input and output timings are measured at the pin. See Figure 8.
2. All maximum timing specifications assume C
L
= 50 pF.
3. This minimum parameter assumes C
L
= 0 pF.
4. SYSCLK to output valid (5.5V to 0.8V) includes the extra delay associated with discharging the external voltage from 5.5V to
0.8V instead of from V
DD
to 0.8V (5V CMOS levels instead of 3.3V CMOS levels).
MODE PINS
HRESET
10c
11c
VM = Midpoint Voltage (1.4V)
VM
Table 13.
Output AC Timing Specifications
(1)(2)
V
DD
= A
V
DD
= 2.5V ± 5%; O
V
DD
= 3.3 ± 5%V, GND = 0V, C
L
= 50 pF, -55
°
C
≤
T
C
≤
125
°
C
Num
Characteristic
166, 200 MHz
233, 266 MHz
300 MHz
Unit
Note
Min
Max
Min
Max
Min
Max
12
SYSCLK to output driven (output enable time)
1.0
-
1.0
-
1.0
-
ns
13a
SYSCLK to output valid (5.5V to 0.8V
—
TS, ABB,
ARTRY, DBB)
-
9.0
-
9.0
-
9.0
ns
4
13b
SYSCLK to output valid (TS, ABB, ARTRY, DBB)
-
8.0
-
8.0
-
8.0
ns
6
14a
SYSCLK to output valid (5.5V to 0.8V
—
all except TS,
ABB, ARTRY, DBB)
-
11.0
-
11.0
-
11.0
ns
4
14b
SYSCLK to output valid (all except
TS,ABB,ARTRY,DBB)
-
9.0
-
9.0
-
9.0
ns
6
15
SYSCLK to output invalid (output hold)
1.0
-
1.0
-
1.0
-
ns
3
16
SYSCLK to output high impedance (all except ARTRY,
ABB, DBB)
-
8.5
-
8.0
-
8.0
ns
17
SYSCLK to ABB, DBB, high impedance after
precharge
-
1.0
-
1.0
-
1.0
t
SYSC
LK
5, 7
18
SYSCLK to ARTRY high impedance before precharge
-
8.0
-
7.5
-
7.5
ns
19
SYSCLK to ARTRY precharge enable
0.2 *
t
SYSC
LK
+ 1.0
-
0.2 *
t
SYSC
LK
+ 1.0
-
0.2 *
t
SYSC
LK
-
ns
3, 5,
8
20
Maximum delay to ARTRY precharge
-
1.0
-
1.0
-
1.0
t
SYSC
LK
5, 8
21
SYSCLK to ARTRY high impedance after precharge
-
2.0
-
2.0
-
2.0
t
SYSC
LK
6, 8
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