參數(shù)資料
型號: TSPC603R
英文描述: TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz
中文描述: TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫
文件頁數(shù): 22/44頁
文件大?。?/td> 636K
代理商: TSPC603R
22
TSPC603R
2125A
HIREL
04/02
Figure 11.
Boundary-scan Timing Diagram
Figure 12.
Test Access Port Timing Diagram
Functional Description
PowerPC Registers and
Programming Model
The PowerPC architecture defines register-to-register operations for most computa-
tional instructions. Source operands for these instructions are accessed from the
registers or are provided as immediate values embedded in the instruction opcode. The
three-register instruction format allows specification of a target register distinct from the
two source operands. Load and store instructions transfer data between registers and
memory.
PowerPC processors have two levels of privilege - supervisor mode of operation (typi-
cally used by the operating system) and user mode of operation (used by the application
software). The programming models incorporate 32 GPRs, 32 FPRs, special-purpose
registers (SPRs) and several miscellaneous registers. Each PowerPC microprocessor
also has its own unique set of hardware implementation (HID) registers.
Input Data Valid
Output Data Valid
Output Data Valid
TCK
Data Inputs
Data Outputs
Data Outputs
Data Outputs
6
7
8
8
9
VM
VM
Input Data Valid
Output Data Valid
Output Data Valid
TCK
TDI, TMS
TDO
TDO
TDO
10
11
12
12
13
VM
VM
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