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參數(shù)資料
| 型號： | TSPC603R |
| 英文描述： | TSPC603R [Updated 4/02. 44 Pages] 32-bit RISC Microprocessor. 166-300 MHz |
| 中文描述： | TSPC603R [更新4 / 02。 44頁] 32位RISC微處理器。 166-300兆赫 |
| 文件頁數(shù)： | 23/44頁 |
| 文件大小： | 636K |
| 代理商： | TSPC603R |
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TSPC603R
2125A
–
HIREL
–
04/02
Having access to privilege instructions, registers, and other resources allows the operat-
ing system to control the application environment (providing virtual memory and
protecting operating-system and critical machine resources). Instructions that control
the state of the processor, the address translation mechanism, and supervisor registers
can be executed only when the processor is operating in supervisor mode.
The following sections summarize the PowerPC registers that are implemented in the
603r.
General-Purpose Registers
(GPRs)
The PowerPC architecture defines 32 user-level, general-purpose registers (GPRs).
These registers are either 32 bits wide in 32-bit PowerPC microprocessors and 64 bits
wide in 64-bit PowerPC microprocessors. The GPRs serve as the data source or desti-
nation for all integer instructions.
Floating-Point Registers
(FPRs)
The PowerPC architecture also defines 32 user-level, 64-bit floating-point registers
(FPRs). The FPRs serve as the data source or destination for floating-point instructions.
These registers can contain data objects of either single- or double-precision float-
ing-point formats.
Condition Register (CR)
The CR is a 32-bit user-level register that consists of eight four-bit fields that reflect the
results of certain operations, such as move, integer and floating-point compare, arith-
metic, and logical instructions, and provide a mechanism for testing and branching.
Floating-Point Status and
Control Register (FPSCR)
The floating-point status and control register (FPSCR) is a user-level register that con-
tains all exception signal bits, exception summary bits, exception enable bits, and
rounding control bits needed for compliance with the IEEE 754 standard.
Machine State Register (MSR)
The machine state register (MSR) is a supervisor-level register that defines the state of
the processor. The contents of this register are saved when an exception is taken and
restored when the exception handling completes. The 603r implements the MSR as a
32-bit register, 64-bit PowerPC processors implement a 64-bit MSR.
Segment Registers (SRs)
For memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit
segment registers (SRs). To speed access, the 603r implements the segment registers
as two arrays; a main array (for data memory accesses) and a shadow array (for instruc-
tion memory accesses). Loading a segment entry with the Move to Segment Register
(STSR) instruction loads both arrays.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMG10LC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
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