參數(shù)資料
型號: TPS65010RGZ
廠商: Texas Instruments, Inc.
英文描述: POWER AND BATTERY MANAGEMENT IC FOR Li-ION POWERED SYSTEMS
中文描述: 電源和電池管理集成電路鋰離子供電系統(tǒng)
文件頁數(shù): 48/50頁
文件大?。?/td> 1006K
代理商: TPS65010RGZ
www.ti.com
IRMSC(out)
VO
1–
VO
VI
L
1
2
3
(5)
VO
VO
1–
VO
VI
L
1
8
CO
ESR
(6)
Input Capacitor Selection
Because of the nature of the buck converter, having a pulsating input current a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. The main converter needs a 22-μF ceramic input capacitor and the core converter a 10-μF
ceramic capacitor. The input capacitor for the main and the core converter can be combined and one 22-μF
capacitor can be used instead, because the two converters operate with a phase shift of 270 degrees. The input
capacitor can be increased without any limit for better input voltage filtering. The VCC pin should be separated
from the input for the main and the core converter. A filter resistor of up to 100R and a 1-μF capacitor is used for
decoupling the VCC pin from switching noise.
LDO1
Output Voltage Adjustment
The output voltage of LDO1 is set with a resistor divider at the feedback pin. The sum of the two resistors must
not exceed 1 MR to minimize voltage changes due to leakage current into the feedback pin. The output voltage
for LDO1 after start up is the voltage set by the external resistor divider. It can be reprogrammed with the I
2
C
interface to the three other values defined in the register VREGS1.
TPS65010
SLVS149A–JUNE 2003–REVISED JANUARY 2004
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meet the application
requirements. Just for completeness the RMS ripple current is calculated as:
At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
Where the highest output voltage ripple occurs at the highest input voltage V
I
.
At light load currents, the converters operate in power save mode and the output voltage ripple is independent of
the output capacitor value. The output voltage ripple is set by the internal comparator thresholds. The typical
output voltage ripple is 1% of the nominal output voltage. If the output voltage for the core converter is
programmed to its lowest voltage of 0.85 V, the output capacitor must be increased to 22 μF for low output
voltage ripple. This is because the current in the inductor decreases slowly during the off-time and further
increases the output voltage even when the PMOS is off. This effect increases with low output voltages.
Table 4. Possible Capacitors
CAPACITOR VALUE
22 μF
22 μF
22 μF
CASE SIZE
1206
1206
1210
COMPONENT SUPPLIER
TDK C3216X5R0J226M
Taiyo Yuden JMK316BJ226ML
Taiyo Yuden JMK325BJ226MM
COMMENTS
Ceramic
Ceramic
Ceramic
48
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