參數(shù)資料
型號(hào)： TPS65010RGZ
廠商： Texas Instruments, Inc.
英文描述： POWER AND BATTERY MANAGEMENT IC FOR Li-ION POWERED SYSTEMS
中文描述： 電源和電池管理集成電路鋰離子供電系統(tǒng)
文件頁(yè)數(shù)： 23/50頁(yè)
文件大?。?/td> 1006K
代理商： TPS65010RGZ
www.ti.com
I(skipmain)
VI(MAIN)
17
I(skipcore)
VI(CORE)
42
(1)
PFM Mode at Light Load
Comp High
Comp Low
Comp Low 2
PFM Mode at Medium to Full Load
1.6%
0.8%
V
O
Forced PWM
Dynamic Voltage Positioning
Soft Start
TPS65010
SLVS149A–JUNE 2003–REVISED JANUARY 2004
During the power save mode the output voltage is monitored with the comparator by the thresholds comp low
and comp high. As the output voltage falls below the comp low threshold, set to typically 0.8% above the nominal
V
out
, the P-channel switch turns on. The converter then runs at 50% of the nominal switching frequency. If the
load is below the delivered current then the output voltage rises until the comp high threshold is reached,
typically 1.6% above the nominal V
out
, whereupon all switching activity ceases, hence reducing the quiescent
current to a minimum until the output voltage has dropped below comp low again. If the load current is greater
than the delivered current, then the output voltage falls until it crosses the nominal output voltage threshold
(comp low 2 threshold), whereupon power save mode is exited and the converter returns to PWM mode.
These control methods reduce the quiescent current to typically to 12-μA per converter and the switching
frequency to a minimum achieving the highest converter efficiency. Setting the comparator thresholds to typically
0.8% and 1.6% above the nominal output voltage at light load current results in a dynamic voltage positioning
achieving lower absolute voltage drops during heavy load transient changes. This allows the converters to
operate with a small output capacitor of just 10 μF for the core and 22 μF for the main output and still have a low
absolute voltage drop during heavy load transient changes. Refer to Figure 30 for detailed operation of the power
save mode. The power save mode can be disabled through the I
2
C interface to force the converters to stay in
fixed frequency PWM mode.
Figure 30. Power Save Mode Thresholds and Dynamic Voltage Positioning
The core and main converters are forced into PWM mode by setting bit 7 in the VDCDC1 register. This feature is
used to minimize ripple on the output voltages.
As described in the power save mode operation sections and as detailed in Figure 13, the output voltage is
typically 1.2% above the nominal output voltage at light load currents as the device is in power save mode. This
gives additional headroom for the voltage drop during a load transient from light load to full load. During a load
transient from full load to light load the voltage overshoot is also minimized due to active regulation turning on the
N-channel rectifier switch.
Both converters have an internal soft start circuit that limits the inrush current during start-up. The soft start is
implemented as a digital circuit increasing the switch current in 4 steps up to the typical maximum switch current
limit of 700 mA (core) and 1.75 A (main). Therefore, the start-up time mainly depends on the output capacitor
and load current.
23
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