參數(shù)資料
型號: TPS65010RGZ
廠商: Texas Instruments, Inc.
英文描述: POWER AND BATTERY MANAGEMENT IC FOR Li-ION POWERED SYSTEMS
中文描述: 電源和電池管理集成電路鋰離子供電系統(tǒng)
文件頁數(shù): 24/50頁
文件大?。?/td> 1006K
代理商: TPS65010RGZ
www.ti.com
100% Duty Cycle Low Dropout Operation
VI(min)
VO(max)
IO(max)
rDS(on)max
RL
(2)
Active Discharge When Disabled
Power Good Monitoring
Overtemperature Shutdown
LOW-DROPOUT VOLTAGE REGULATORS
The low-dropout voltage regulators are designed to operate with low value ceramic input and output capacitors.
They operate with input voltages down to 1.8 V. The LDOs offer a maximum dropout voltage of 300 mV at rated
output current. Each LDO sports a current limit feature. Both LDOs are enabled per default, both LDOs can be
disabled or programmed via the serial interface using the VREGS1 register. The LDO outputs (when enabled)
are monitored by power good comparators, the outputs of which are available via the serial interface. The LDOs
also have reverse conduction prevention when disabled. This allows the possibility to connect external regulators
in parallel in systems with a backup battery.
Power Good Monitoring
TPS65010
SLVS149A–JUNE 2003–REVISED JANUARY 2004
The TPS65010 converters offer a low input to output voltage difference while maintaining operation with the use
of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole
battery voltage range. i.e., The minimum input voltage to maintain regulation depends on the load current and
output voltage and is calculated as:
with:
I
O(max)
= maximum output current plus inductor ripple current
r
DS(on)max
= maximum P-channel switch r
DSon
.
R
L
= DC resistance of the inductor
V
O(max)
= nominal output voltage plus maximum output voltage tolerance
When the CORE and MAIN converters are disabled, due to an UVLO, BATT_COVER or OVERTEMP condition,
it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled via
the VDCDC1 and VDCDC2 registers in the serial interface. When this feature is enabled, the core and main
outputs are discharged by a 400-
(typical) load.
Both the MAIN and CORE converters have power good comparators. Each comparator indicates when the
relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these
comparators are available in the REGSTATUS register via the serial interface. A maskable interrupt is generated
when any voltage rail drops below the 10% threshold. The comparators are disabled when the converters are
disabled.
The MAIN and CORE converters are automatically shut down if the temperature exceeds the trip point (see the
electrical characteristics). This detection is only active if the converters are in PWM mode, either by setting
FPWM = 1, or if the output current is high enough that the device runs in PWM mode automatically.
Both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the
relevant output voltage has dropped 10% below it's target value, with 5% hysteresis. The outputs of these
comparators are available in the REGSTATUS register via the serial interface. An interrupt is generated when
any voltage rail drops below the 10% threshold. The LDO2 comparator is disabled when LDO2 is disabled. The
LDO1 power good comparator is always active since it generates the system reset signal, RESPWRON, see the
System Reset and Control Signal Section below. This also allows the possibility to monitor VLDO1, even if it is
provided by an external regulator.
24
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