參數(shù)資料
型號(hào): TPS65010RGZ
廠商: Texas Instruments, Inc.
英文描述: POWER AND BATTERY MANAGEMENT IC FOR Li-ION POWERED SYSTEMS
中文描述: 電源和電池管理集成電路鋰離子供電系統(tǒng)
文件頁(yè)數(shù): 44/50頁(yè)
文件大?。?/td> 1006K
代理商: TPS65010RGZ
www.ti.com
VDCDC2 Register (Address: 0Dh—Default Value: 60h/70h)
TPS65010
SLVS149A–JUNE 2003–REVISED JANUARY 2004
Bit 4 - ENABLE SUPPLY:
0 = not allowed
1 = must be left set.
Bit 3 - ENABLE LP:
0 = disables the low power function of the LOW_PWR pin.
1 = enables the low power function of the LOW_PWR pin.
Bit 2 - MAIN DISCHARGE:
0 = disable the active discharge of the VMAIN converter output.
1 = enable the active discharge of the VMAIN converter output, when the converter is disabled.
Bit 1-Bit 0 - MAIN<1:0>: The VMAIN converter output voltages are set according to the following table, with the
default values in bold set by the DEFMAIN pin. The default voltage can subsequently be over-written via the
serial interface after start-up.
MAIN1
0
0
1
1
MAIN0
0
1
0
1
VMAIN
2.5 V
2.75 V
3.0 V
3.3 V
VDCDC2
B7
B6
B5
B4
B3
B2
B1
B0
CORE
Bit name
LP_COREOFF
CORE2
CORE1
CORE0
CORELP1
CORELP0
VIB
DISCHARGE
Default
0
1
1
DEFCORE
1
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8
steps between 0.85 V and 1.6 V. The default value is governed by the DEFCORE pin; DEFCORE=0 sets an
output voltage of 1.5 V. DEFCORE=1 sets an output voltage of 1.6 V.
Bit 7 - LP_COREOFF:
0 = VCORE converter is enabled in low power mode.
1 = VCORE converter is disabled in low power mode.
Bit 6-Bit 4 - CORE<2:0>: The following table shows all possible values of VCORE. The default value can
subsequently be overwritten via the serial interface after start-up.
CORE2
0
0
0
0
1
1
1
1
CORE1
0
0
1
1
0
0
1
1
CORE0
0
1
0
1
0
1
0
1
VCORE
0.85 V
1.0 V
1.1 V
1.2 V
1.3 V
1.4 V
1.5 V
1.6 V
Bit 3-Bit 2 - CORELP<1:0>: CORELP1 and CORELP0 can be used to set the VCORE voltage in low power
mode. In low power mode, CORE2 is effectively '0', and CORE1, CORE0 take on the values programmed at
CORELP1 and CORELP0, default '10' giving VCORE = 1.1V as default in low power mode. When low power
mode is exited, VCORE reverts to the value set by CORE2, CORE1 & CORE0.
Bit 1 - VIB:
0 = disables the VIB output transistor.
44
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