參數(shù)資料
型號(hào)： TPS65010RGZ
廠商： Texas Instruments, Inc.
英文描述： POWER AND BATTERY MANAGEMENT IC FOR Li-ION POWERED SYSTEMS
中文描述： 電源和電池管理集成電路鋰離子供電系統(tǒng)
文件頁(yè)數(shù)： 36/50頁(yè)
文件大小： 1006K
代理商： TPS65010RGZ
www.ti.com
SERIAL INTERFACE
The serial interface is compatible with the standard and fast mode I
2
C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as V
CC
remains above 2 V. The TPS65010 has a 7-bit address with the
LSB set by the IFLSB pin, this allows the connection of two devices with the same address to the same bus. The
6 MSBs are 100100. Attempting to read data from register addresses not listed in this section results in FFh
being read out.
TPS65010
SLVS149A–JUNE 2003–REVISED JANUARY 2004
The following describes the function of the 0x05 (ACKINT1) and 0x06 (ACKINT2) registers. These are not
usually written to by the CPU since the TPS65010 internally sets/clears these registers:
ACKINT1(7:0) - Bit is set when the corresponding CHGSTATUS set bit is read via I
2
C.
ACKINT1(7:0) - Bit is cleared when the corresponding CHGSTATUS set bit clears.
ACKINT2(7:0) - Bit is set when the corresponding REGSTATUS set bit is read via I
2
C.
ACKINT2(7:0) - Bit is cleared when the corresponding REGSTATUS set bit clears.
ACKINT1(7:0) - a bit set masks the corresponding CHGSTATUS bit from INT.
ACKINT2(7:0) - a bit set masks the corresponding REGSTATUS bit from INT.
The following describes the function of the 0x03 (MASK1), 0x04 (MASK2) and 0x0F (MASK3) registers:
MASK1(7:0) - a bit set in this register masks CHGSTATUS from INT.
MASK2(7:0) - a bit set in this register masks REGSTATUS from INT.
MASK3(7:4) - a bit set in this register detects a rising edge on GPIO.
MASK3(7:4) - a bit cleared in this register detects a falling edge on GPIO.
MASK3(3:0) - a bit set in this register clears GPIO Detect signal from INT.
GPIO interrupts are located by reading the 0x10 (DEFGPIO) register. The application CPU stores, or can read
from DEFGPIO<7:4>, which GPIO is set to input or output. This information together with the information on
which edge the interrupt was generated (the CPU either knows this or can read it from MASK3<7:4>) determines
whether the CPU is looking for a 0 or a 1 in DEFGPIO<3:0>. A GPIO interrupt is blocked from the INT pin by
setting the relevant MASK3<3:0> bit; this must be done by the CPU, there is no auto-acknowledge for the GPIO
interrupts.
REGSTATUS(3-0) are level set. Read of set REGSTATUS(3-0) bits sets ACKINT2(3-0) bits.
REGSTATUS(7-5) clear when input signal low and ACKINT1(7-5) bit are already set.
REGSTATUS(3-0) clear when input signal is low.
ACKINT2(7-0) clear when REGSTATUS(7-0) is clear.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65010 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65010 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS65010 device must leave the data line high to enable the master to generate the stop
condition.
36
相關(guān)PDF資料
PDF描述
TPS65011RGZ POWER AND BATTERY MANAGEMENT IC FOR Li-ION POWERED SYSTEMS
TPS65013RGZ POWER AND BATTERY MANAGEMENT IC FOR Li-ION POWERED SYSTEMS
TPS65020RHA POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS
TPS65100RGE TRIPLE OUTPUT LCD SUPPLY WITH LINEAR REGULATOR AND VCOM BUFFER
TPS65105RGE TRIPLE OUTPUT LCD SUPPLY WITH LINEAR REGULATOR AND VCOM BUFFER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TPS65010RGZR 功能描述:電池管理 Multi-Channel 1-cell Li-Ion RoHS:否 制造商:Texas Instruments 電池類(lèi)型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel
TPS65010RGZRG4 功能描述:電池管理 Multi-Channel 1-cell Li-Ion RoHS:否 制造商:Texas Instruments 電池類(lèi)型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel
TPS65010RGZT 功能描述:電池管理 Multi-Channel 1-cell Li-Ion RoHS:否 制造商:Texas Instruments 電池類(lèi)型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel
TPS65010RGZTG4 功能描述:電池管理 Multi-Channel 1-cell Li-Ion RoHS:否 制造商:Texas Instruments 電池類(lèi)型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel
TPS65011EVM-049 功能描述:電源管理IC開(kāi)發(fā)工具 TPS65011-049 Eval Mod RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類(lèi)型:Battery Management 工具用于評(píng)估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*