參數(shù)資料
型號: TPS65010RGZ
廠商: Texas Instruments, Inc.
英文描述: POWER AND BATTERY MANAGEMENT IC FOR Li-ION POWERED SYSTEMS
中文描述: 電源和電池管理集成電路鋰離子供電系統(tǒng)
文件頁數(shù): 43/50頁
文件大?。?/td> 1006K
代理商: TPS65010RGZ
www.ti.com
LED2_ON Register (Address: 0Ah—Default Value: 00h)
LED2_PER (Register Address: 0Bh—Default Value: 00h)
VDCDC1 Register (Address: 0Ch—Default Value: 72h/73h)
TPS65010
SLVS149A–JUNE 2003–REVISED JANUARY 2004
Bit 6-Bit 0 - LED1_PER<6:0> are used to program the time period of the open drain output transistor at the PG
pin. The minimum period is typically 100 ms and one LSB corresponds to a 100-ms step change in the period.
LED2_ON
Bit name
Default
Read/write
B7
B6
B5
B4
B3
B2
B1
B0
LED21
0
R/W
LED2 ON6
0
R/W
LED2 ON5
0
R/W
LED2 ON4
0
R/W
LED2 ON3
0
R/W
LED2 ON2
0
R/W
LED2 ON1
0
R/W
LED2 ON0
0
R/W
The LED2_ON and LED2_PER registers are used to control the LED2 open drain output.
Bit 7 LED22: Control is determined by LED21 and LED22 according to the table under LED2_PER register.
Bit 6-Bit 0 - LED2_ON<6:0> are used to program the on-time of the open drain output transistor at the LED2 pin.
The minimum on time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on time.
LED2_PER
Bit name
Default
Read/write
B7
B6
B5
B4
B3
B2
B1
B0
LED22
0
R/W
LED2 PER6
0
R/W
LED2 PER5
0
R/W
LED2 PER4
0
R/W
LED2 PER3
0
R/W
LED2 PER2
0
R/W
LED2 PER1
0
R/W
LED2 PER 0
0
R/W
Bit 7 LED22: Control is determined by LED21 and LED22 according to the table. Default shown in
bold
.
Bit 6-Bit 0 - LED2_ON<6:0> are used to program the on-time of the open drain output transistor at the LED2 pin.
The minimum on time is typically 100 ms and one LSB corresponds to a 100-ms step change in the on time.
LED21
0
0
1
1
LED22
0
1
0
1
BEHAVIOR OF LED2 OPEN DRAIN OUTPUT
Off
Blink
Off
Always On
VDCDC1
Bit name
B7
B6
B5
B4
B3
B2
B1
B0
FPWM
UVLO1
UVLO0
ENABLE
SUPPLY
1
R/W
ENABLE
LP
0
R/W
MAIN DIS-
CHARGE
0
R/W
MAIN1
MAIN0
Default
Read/write
0
1
1
1
DEFMAIN
R/W
R/W
R/W
R/W
R/W
The VDCDC1 register is used to program the VMAIN switching converter.
Bit 7 - FPWM: forced PWM mode for dc-dc converters.
0 = MAIN and the CORE dc-dc converter are allowed to switch into PFM mode.
1 = MAIN and the CORE dc-dc converter operate with forced fixed frequency PWM mode and are not
allowed to switch into PFM mode at light load.
Bit 6-Bit 5 - UVLO<1:0>: The under-voltage threshold voltage is set by UVLO1 and UVLO0 according to the
below table, with the default value in
bold
.
UVLO1
0
0
1
1
UVLO0
0
1
0
1
V
UVLO
2.5 V
2.75 V
3.0 V
3.25 V
43
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