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6.4.1
Reset Electrical Data/Timing
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 6-8. Timing Requirements for Reset (see
Figure 6-9
)
-594
NO.
UNIT
MIN
MAX
1
2
3
t
w(RST)
t
su(BOOT)
t
h(BOOT)
Width of the RESET pulse
Setup time, boot configuration bits valid before RESET high
Hold time, boot configuration bits valid after RESET high
444
444
444
ns
ns
ns
Table 6-9. Switching Characteristics Over Recommended Operating Conditions During Reset
(1)
(see
Figure 6-9
)
-594
NO.
UNIT
MIN
MAX
2000P
2P + 20
26
4
5
6
16
17
7
8
9
18
19
24
10
11
12
20
21
13
14
15
22
23
25
t
d(PLL_LOCK)
t
d(RSTL-DDRZZ)
t
d(RSTL-DDRLL)
t
d(RSTL-DDRHH)
t
d(RSTL-DDRZHZ)
t
d(RSTL-DDRLHL)
t
d(RSTL-ZZ)
t
d(RSTL-LOWL)
t
d(RSTL-HIGHH)
t
d(RSTL-HIGHLOWH)
t
d(RSTL-LOWHIGHL)
t
d(RSTL-ZIZ)
t
d(RSTH-DDRZV)
t
d(RSTH-DDRLV)
t
d(RSTH-DDRHV)
t
d(RSTH-DDRZHV)
t
d(RSTH-DDRLHV)
t
d(RSTH-ZV)
t
d(RSTH-LOWV)
t
d(RSTH-HIGHV)
t
d(RSTH-HIGHLOWV)
t
d(RSTH-LOWHIGHV)
t
d(RSTH-ZIIV)
P = MXI/CLKIN cycle time, in ns.
Following RESET high, this signal group maintains the state the pins(s) achieved while RESET was driven low until the peripheral is
enabled via the PSC. For example, the DDR2 Z Group goes high impedance following RESET low and remains in the high-impedance
state following RESET high until the DDR2 controller is enabled via the PSC.
Delay time, PLL1 lock time
Delay time, RESET low to DDR2 Z Group high impedance
Delay time, RESET low to DDR2 Low Group low
Delay time, RESET low to DDR2 High Group high
Delay time, RESET low to DDR2 Z/High Group high impedance
Delay time, RESET low to DDR2 Low/High Group low
Delay time, RESET low to Z Group high impedance
Delay time, RESET low to Low Group low
Delay time, RESET low to High Group high
Delay time, RESET low to High/Low Group high
Delay time, RESET low to Low/High Group low
Delay time, RESET low to Z/Invalid Group high impedance
Delay time, RESET high to DDR2 Z Group valid
Delay time, RESET high to DDR2 Low Group valid
Delay time, RESET high to DDR2 High Group valid
Delay time, RESET high to DDR2 Z/High Group valid high
Delay time, RESET high to DDR2 Low/High Group valid high
Delay time, RESET high to Z Group valid
Delay time, RESET high to Low Group valid
Delay time, RESET high to High Group valid
Delay time, RESET high to High/Low Group valid low
Delay time, RESET high to Low/High Group valid high
Delay time, RESET high to Z/Invalid Group invalid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
0
0
0
0
0
0
0
20
20
5P + 20
20
20
20
20
20
20
20
(2)
(2)
(2)
4000P
4000P
(2)
(2)
(2)
5100P
5100P
4000P
(1)
(2)
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