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| 型號(hào)： | TMX320DM6443ZWT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media System-on-Chip |
| 中文描述： | 數(shù)字媒體系統(tǒng)片上 |
| 文件頁(yè)數(shù)： | 136/221頁(yè) |
| 文件大?。?/td> | 1582K |
| 代理商： | TMX320DM6443ZWT |
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TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 6-35. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module
(1)(2)
(see
Figure 6-21
and
Figure 6-22
)
-594
NO.
PARAMETER
UNIT
MIN
MAX
READS and WRITES
1
t
d(TURNAROUND)
Turn around time
(TA + 1) * E - 2
(TA + 1) * E + 2
ns
READS
(RS + RST + RH +
TA + 4) * E - 0.5
(RS + RST + RH +
TA + 4) * E - 0.5
(RS + RST + RH + TA +
EMIF read cycle time (EW = 0)
ns
4) * E + 0.5
3
t
c(EMRCYCLE)
EMIF read cycle time (EW = 1)
4184 * E + 0.5
ns
Output setup time, EM_CS[5:2] low to EM_OE low (SS
= 0)
Output setup time, EM_CS[5:2] low to EM_OE low (SS
= 1)
Output hold time, EM_OE high to EM_CS[5:2] high
(SS = 0)
Output hold time, EM_OE high to EM_CS[5:2] high
(SS = 1)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[21:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[21:0] invalid
EM_OE active low width (EW = 0)
EM_OE active low width (EW = 1)
Delay time from EM_WAIT deasserted to EM_OE high
(RS + 1) * E - 1
(RS + 1) * E + 1.2
ns
4
t
su(EMCSL-EMOEL)
-1
ns
(RH + 1) * E - 1.3
(RH + 1) * E + 1.4
ns
5
t
h(EMOEH-EMCSH)
-1.4
ns
6
7
8
9
t
su(EMBAV-EMOEL)
t
h(EMOEH-EMBAIV)
t
su(EMAV-EMOEL)
t
h(EMOEH-EMAIV)
(RS + 1) * E - 1.8
(RH + 1) * E - 2.1
(RS + 1) * E - 1.9
(RH + 1) * E - 2.4
(RST + 1) * E - 2
(RST + 1) * E - 2
(RS + 1) * E + 1.3
(RH + 1) * E + 1.1
(RS + 1) * E + 1.5
(RH + 1) * E + 1.2
(RST + 1) * E + 2
(RST + 4097) * E + 2
ns
ns
ns
ns
ns
ns
ns
10
t
w(EMOEL)
11
t
d(EMWAITH-EMOEH)
4E + 10.4
WRITES
(WS + WST + WH
+ TA + 4) * E - 0.5
(WS + WST + WH
+ TA + 4) * E -0.5
(WS + WST + WH + TA
+ 4) * E + 0.5
EMIF write cycle time (EW = 0)
ns
15
t
c(EMWCYCLE)
EMIF write cycle time (EW = 1)
4184 * E + 0.5
ns
Output setup time, EM_CS[5:2] low to EM_WE low
(SS = 0)
Output setup time, EM_CS[5:2] low to EM_WE low
(SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high
(SS = 0)
Output hold time, EM_WE high to EM_CS[5:2] high
(SS = 1)
Output setup time, EM_R/W valid to EM_WE low
Output hold time, EM_WE high to EM_R/W invalid
Output setup time, EM_BA[1:0] valid to EM_WE low
Output hold time, EM_WE high to EM_BA[1:0] invalid
Output setup time, EM_A[21:0] valid to EM_WE low
Output hold time, EM_WE high to EM_A[21:0] invalid
EM_WE active low width (EW = 0)
EM_WE active low width (EW = 1)
Delay time from EM_WAIT deasserted to EM_WE high
(WS + 1) * E - 0.9
(WS + 1) * E + 1.4
ns
16
t
su(EMCSL-EMWEL)
-1
ns
(WH + 1) * E - 1.4
(WH + 1) * E + 1.1
ns
17
t
h(EMWEH-EMCSH)
-1.4
ns
18
19
20
21
22
23
t
su(EMRNW-EMWEL)
t
h(EMWEH-EMRNW)
t
su(EMBAV-EMWEL)
t
h(EMWEH-EMBAIV)
t
su(EMAV-EMWEL)
t
h(EMWEH-EMAIV)
(WS + 1) * E - 0.7
(WH + 1) * E - 0.9
(WS + 1) * E - 1.7
(WH + 1) * E - 2.2
(WS + 1) * E - 1.8
(WH + 1) * E - 2.5
(WST + 1) * E - 2
(WST + 1) * E - 2
(WS + 1) * E + 0.9
(WH + 1) * E + 0.9
(WS + 1) * E + 1.5
(WH + 1) * E + 0.9
(WS + 1) * E + 1.7
(WH + 1) * E + 1
(WST + 1) * E + 2
(WST + 4097) * E + 2
ns
ns
ns
ns
ns
ns
ns
24
t
w(EMWEL)
25
t
d(EMWAITH-EMWEH)
4E + 10.4
ns
(1)
RS = Read setup, RST = Read STrobe, RH = Read Hold, WS = Write Setup, WST = Write STrobe, WH = Write Hold, TA = Turn
Around, EW = Extend Wait mode, SS = Select Strobe mode. These parameters are programmed via the Asynchronous Bank and
Asynchronous Wait Cycle Configuration Registers and support the following range of values: TA[3:0], RS[15:0], RST[63:0], RH[7:0],
WS[15:0], WST[63:0], WH[7:0], and EW[255:0]. For more information, see the
TMS320DM644x DMSoC Asynchronous External Memory
Interface (EMIF) User's Guide
(literature number
SPRUE20
).
E = SYSCLK5 period in ns for EMIFA. For example, when running the DSP CPU at 594 MHz, use E = 10.1 ns.
(2)
Peripheral and Electrical Specifications
136
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