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CV
DD
CV
DDDSP
CV
DD
DV
DDXX
(A)
Note A: DV
denotes all I/O supplies.
DDXX
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 6-1. Core Supply Power-On Timing Requirements for DSP Host-Boot Mode (see
Figure 6-4
)
-594
NO.
UNIT
MIN
MAX
1
t
d(CVDD-CVDDDSP)
In Host-Boot mode, the CV
DDDSP
supply
must
be powered up prior to closing (enabling) the shorting switch between the ALWAYS ON
and DSP power domains.
Delay time, CV
DD
supply ready to CV
DDDSP
supply ramp start
0
(1)
ns
(1)
Figure 6-4. DSP Host-Boot Mode Core Supply Timings
Once the CV
DD
supply has been powered up, the I/O supplies may be powered up.
Table 6-2
and
Figure 6-5
show the power-on sequence timing requirements for the Core vs. I/O power-up. DV
DDXX
is
used to denote all I/O supplies. Note: the DV
DDXX
supply power-up is specified relative to the CV
DD
supply
power-up, not the CV
DDDSP
supply.
Table 6-2. I/O Supply Power-On Timing Requirements (see
Figure 6-5
)
-594
NO.
UNIT
MIN
MAX
100
1
t
d(CVDD-DVDD)
Delay time, CV
DD
supply ready to DV
DDXX
supply ramp start
0
ms
Figure 6-5. I/O Supply Timings
There is
not
a specific power-up sequence that must be followed with respect to the order of the power-up
of the DV
DD18
, DV
DDR2
, and DV
DD33
supplies. Once the CV
DD
supply is powered up and the t
d(CVDD-DVDDXX)
specification is met, the DV
DD18
, DV
DDR2
, and DV
DD33
supplies may be powered up in any order of
preference. All other supplies may also be powered up in any order of preference once the t
d(CVDD-DVDDXX)
specification has been met.
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