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3
4
1
RESET
Boot
Configuration Pins
2
10
11
5
DDR2 Low Group
(A)
DDR2 Z Group
(A)
12
6
DDR2 High Group
(A)
16
20
21
17
DDR2 Low/High Group
(A)
DDR2 Z/High Group
(A)
A.
DDR2 Z Group:
DDR_DQS[3:0], DDR_D[12:0]
DDR2 Low Group:
DDR_CLK0, DDR_CKE, DDR_A[12:0]
DDR2 High Group:
DDR_CLK0, DDR_CS, DDR_WE, DDR_RAS, DDR_CAS
DDR2 Z/High Group:
DDR_DQM[3:0],
DDR2 Low/High Group:
DDR_BS[2:0]
Low Group:
DMARQ/UART_RXD1, VCLK, RTCK, TDO, VPBECLK, YOUT0/G5/AEAW0, YOUT1/G6/AEAW1,
YOUT2/G7/AEAW2, YOUT3/R3/AEAW3, YOUT4/R4/AEAW4, COUT3/B6/DSP_BT, COUT2/B5/EM_WIDTH,
COUT1/B4/BTSEL1, COUT0/B3/BTSEL0, TRST
High Group:
DMACK/UART_TXD1, EM_A[2]/(CLE), EM_A[1]/(ALE), EM_CS3, EM_WE/(WE)(IOWR)/DIOW
Z Group:
All other pins not listed above, with the exception of power and ground pins.
The following Z Group pins have an internal pullup (IPU):
DMARQ/UART_RXD1, VPBECLK, HSYNC, VSYNC,
YOUT0/G5/AEAW0, YOUT1/G6/AEAW1, YOUT2/G7/AEAW2, YOUT3/R3/AEAW3, YOUT4/R4/AEAW4,
COUT3/B6/DSP_BT COUT2/B5/EM_WIDTH, COUT1/B4/BTSEL1, COUT0/B3/BTSEL0, TRST, YI/CCD[7:0],
CI[3:0]/CCD[11:8], CI4/CCD12/UART_RTS2, CI5/CCD13/UART_CTS2, CI6/CCD14/UART_TXD2,
CI7/CCD15/UART_RXD2
The following Z Group pins have an internal pulldown (IPD): EM_WAIT/IORDY, TCK, TDI, TMS, EMU[1:0]
High/Low Group:
EM_BA[0]/DA0, EM_CS2, EM_OE/(RE)/(IORD)/DIOR
Low/High Group:
EM_R/W/INTRQ
Z/Invalid Group:
EM_D[15:0]
7
14
8
Low Group
(A)
Z Group
(A)
15
9
High Group
(A)
13
22
18
High/Low Group
(A)
23
19
Low/High Group
(A)
24
Z/Invalid Group
(A)
25
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Figure 6-9. Reset Timing
100
Peripheral and Electrical Specifications
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