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DMARQ
t
DVH
t
ENV
DSTROBE (IORDY)
(A)
STOP (DIOW)
(A)
HDMARDY (DIOR)
(A)
DD[15:0]
DA[2:0],
ATA_CS0,
ATA_CS1
t
FS
t
ENV
t
ZFS
t
DZFS
t
DVS
t
ZAD
t
ZAD
t
FS
t
UI
t
ACK
t
ACK
t
ZIORDY
t
AZ
t
ACK
DMACK
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 6-41. Timings for ATA/CF Module — Ultra DMA AC Timing
(see
Figure 6-28
through
Figure 6-37
) (continued)
-594
NO.
UNIT
MODE
0-4
0-4
0-4
MIN
0
20
0
MAX
150
15
16
17
t
LI
t
MLI
t
UI
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output drivers to
release
Minimum delay time required for output
Minimum delay time for driver to assert or negate
(from released)
Envelope time, DMACK to STOP and DMACK to
HDMARDY during in-burst initiation and from
DMACK to STOP during data out burst initiation
ns
ns
ns
18
t
AZ
0-4
10
ns
19
t
ZAH
0-4
20
ns
20
t
ZAD
0-4
0
ns
21
t
ENV
0-4
(TENV + 1)P - 0.5
(TENV + 1)P + 1.4
ns
0
1
75
70
60
ns
ns
ns
22
t
RFS
Ready-to-final-STROBE time
2-4
Ready to pause time,
(HDMARDY (DIOR) to
STOP (DIOW))
0-4
(UDMATRP + 1)P - 0.8
ns
0
1
160
125
100
ns
ns
ns
ns
ns
23
t
RP
Ready to pause time,
(DDMARDY (IORDY) to
DMARQ)
2-4
0-4
0-4
24
25
t
IORDYZ
t
ZIORDY
Maximum time before releasing IORDY
Minimum time before driving IORDY
Setup and hold time for DMACK (before
assertion or negation)
STROBE edge to negation of DMARQ or
assertion of STOP (when sender terminates a
burst)
20
0
26
t
ACK
0-4
20
ns
27
t
SS
0-4
50
ns
A.
The definitions for the DIOW:STOP, DIOR:HDMARDY, and IORDY:DSTROBE signal lines are not in effect until
DMARQ and DMACK are asserted.
Figure 6-28. ATA/CF Initiating an Ultra DMA Data-In Burst Timing
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Peripheral and Electrical Specifications
147