
www.ti.com
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Table 2-10. DDR2 Memory Controller Terminal Functions
SIGNAL
NAME
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NO.
DDR2 Memory Controller
DDR2 Clock
DDR2 Differential clock
DDR2 Clock Enable
DDR2 Active low chip select
DDR2 Active low Write enable
DDR_CLK0
DDR_CLK0
DDR_CKE
DDR_CS
DDR_WE
DDR_DQM[3]
DDR_DQM[2]
DDR_DQM[1]
DDR_DQM[0]
DDR_RAS
DDR_CAS
DDR_DQS[0]
DDR_DQS[1]
DDR_DQS[2]
W7
W8
V8
T9
T8
T16
T14
T6
T4
U7
T7
U4
U6
U14
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DDR2 Data mask outputs
DQM3: For upper byte data bus DDR_D[31:24]
DQM2: For DDR_D[23:16]
DQM1: For DDR_D[15:8]
DQM0: For lower byte DDR_D[7:0]
DDR2 Row Access Signal output
DDR2 Column Access Signal output
Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to
the DDR2 memory when writing and inputs when reading. They are used to
synchronize the data transfers.
DQS3 : For upper byte DDR_D[31:24]
DQS2: For DDR_D[23:16]
DQS1: For DDR_D[15:8]
DQS0: For bottom byte DDR_D[7:0]
DDR_DQS[3]
U16
I/O/Z
DV
DDR2
DDR_BS[0]
DDR_BS[1]
DDR_BS[2]
DDR_A[12]
DDR_A[11]
DDR_A[10]
DDR_A[9]
DDR_A[8]
DDR_A[7]
DDR_A[6]
DDR_A[5]
DDR_A[4]
DDR_A[3]
DDR_A[2]
DDR_A[1]
DDR_A[0]
U8
V9
U9
W9
W10
U10
U11
V10
V11
W11
W12
V12
U12
V13
U13
W13
I/O/Z
DV
DDR2
Bank select outputs (BS[2:0]). Two are required to support 1Gb DDR2 memories.
I/O/Z
DV
DDR2
DDR2 address bus
(1)
(2)
(3)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
Specifies the operating I/O supply voltage for each signal
For more information, see the
Recommended Operating Conditions
table
Submit Documentation Feedback
Device Overview
35