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參數(shù)資料
| 型號(hào)： | TMX320DM6443AZWT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media System-on-Chip |
| 中文描述： | 數(shù)字媒體系統(tǒng)片上 |
| 文件頁(yè)數(shù)： | 3/221頁(yè) |
| 文件大?。?/td> | 1582K |
| 代理商： | TMX320DM6443AZWT |
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www.ti.com
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and
C64x+ CPU, respectively.
With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the
C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The
eight functional units include instructions to accelerate the performance in video and imaging applications.
The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million
MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details
on the C64x+ DSP, see the
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide
(literature number SPRU732).
The DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000 DSP platform devices. The DM6443 core uses a two-level
cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the
Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)
consists of an 512K-bit memory space that is shared between program and data space. L2 memory can
be configured as mapped memory, cache, or combinations of the two.
The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a
Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio
serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1
64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable
interrupt/event generation modes, multiplexed with other peripherals;
handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory
interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a
higher speed synchronous memory interface for DDR2.
3
UARTs
with
hardware
The DM6443 includes a Video Processing Sub-System (VPSS) that has a configurable Resizer and Video
Processing Back-End (VPBE) output used for display.
The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments
of 256/N, where N is between 64 and 1024.
The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a
Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate
OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window
allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz,
providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC
also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of
8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644x and
the network. The DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps)
and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS)
support.
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the
MDIO module transparently monitors its link state by reading the PHY status register. Link change events
are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link
status of the device without continuously performing costly MDIO accesses.
The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 to easily control peripheral devices and/or
communicate with host processors. The DM6443 also provides multimedia card support, MMC/SD, with
SDIO support.
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Digital Media System-on-Chip (DMSoC)
3
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| TMX320DM6443ZWT | Digital Media System-on-Chip |
| TMS320DM647_08 | Digital Media Processor |
| TMS320DM647ZUT720 | Digital Media Processor |
| TMS320DM647ZUT900 | Digital Media Processor |
| TMS320DM648ZUT720 | Digital Media Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320DM6443BZWT | 制造商:Texas Instruments 功能描述: |
| TMX320DM6443CZWT | 制造商:Texas Instruments 功能描述: |
| TMX320DM6443ZWT | 制造商:Texas Instruments 功能描述: |
| TMX320DM6444AZWT | 制造商:Texas Instruments 功能描述:TMS320DM6443, TMS320DM6444 DIGITAL MEDIA SOC DATA SHEET - Trays |
| TMX320DM6446AZWT | 制造商:Texas Instruments 功能描述: |
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