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P
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 3-6. Fixed-Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 001b)
DEVICE BOOT AND
CONFIGURATION PINS
PLLC1 CLOCK SETTING AT BOOT
DM6437 DMP
(Master/Slave)
DSPBOOTADDR
(DEFAULT)
(1)
BOOT DESCRIPTION
(1)
DEVICE
FREQUENCY
(SYSCLK1)
PLL
CLKDIV1 DOMAIN
(SYSCLK1 DIVIDER)
BOOTMODE[3:0]
PCIEN
MODE
(2)
0000
0 or 1
No Boot (Emulation Boot)
Master
Bypass
/1
CLKIN
0x0010 0000
HPI Boot with PLL
Multiplier x27 at boot
0
Slave
x27
/2
CLKIN x27 / 2
0x0010 0000
0001
1
Reserved
–
–
–
–
–
HPI Boot with PLL
Multiplier x20 at boot
0
Slave
x20
/2
CLKIN x20 / 2
0x0010 0000
0010
1
Reserved
–
–
–
–
–
HPI Boot with PLL
Multiplier x15 at boot
0
Slave
x15
/2
CLKIN x15 / 2
0x0010 0000
0011
1
Reserved
–
–
–
–
–
EMIFA ROM FASTBOOT
with Application Image
Script (AIS)
0100
0 or 1
Master
x20
/2
CLKIN x20 / 2
0x0010 000
I2C Boot
[FAST MODE]
(3)
0101
0 or 1
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
16-bit SPI Boot
[McBSP0]
0110
0 or 1
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
0111
0 or 1
NAND Flash Boot
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
UART Boot without
Hardware Flow Control
[UART0]
1000
0 or 1
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
EMIFA ROM FASTBOOT
without AIS
1001
0 or 1
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
1010
0 or 1
Reserved
–
–
–
–
–
1011
0 or 1
Reserved
–
–
–
–
–
1100
0 or 1
Reserved
–
–
–
–
–
1101
0 or 1
Reserved
–
–
–
–
–
UART Boot with
Hardware Flow Control
[UART0]
1110
0 or 1
Master
x20
/2
CLKIN x20 / 2
0x0010 0000
1111
0 or 1
Reserved
–
–
–
–
–
(1)
For all boot modes that default to DSPBOOTADDR = 0x0010 0000, the bootloader code disables all C64x+ cache (L2, L1P, and L1D)
so that upon exit from the bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application
code must explicitly enable the cache. For more information on the bootloader, see the
Using the TMS320DM643x Bootloader
Application Report (literature number
SPRAAG0
).
The PLL MODE for Fixed-Multiplier Fastboot Modes is fixed as shown in this table; therefore, the PLLMS[2:0] configuration pins have no
effect on the PLL MODE.
I2C Boot (BOOTMODE[3:0] = 0101b) is
only
available if the MXI/CLKIN frequency is between 21 MHz to 30 MHz. I2C Boot is
not
available for MXI/CLKIN frequencies less than 21 MHz.
(2)
(3)
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Device Configurations
85