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1
Digital Media System-on-Chip (DMSoC)
1.1 Features
High-Performance Digital Media SoC
–
594-MHz C64x+ Clock Rate
–
297-MHz ARM926EJ-S Clock Rate
–
Eight 32-Bit C64x+ Instructions/Cycle
–
4752 C64x+ MIPS
–
Fully Software-Compatible With C64x /
ARM9
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+ DSP Core
–
Eight Highly Independent Functional Units
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
–
Load-Store Architecture With Non-Aligned
Support
–
64 32-Bit General-Purpose Registers
–
Instruction Packing Reduces Code Size
–
All Instructions Conditional
–
Additional C64x+ Enhancements
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
Hardware Support for Modulo Loop
Operation
C64x+ Instruction Set Features
–
Byte-Addressable (8-/16-/32-/64-Bit Data)
–
8-Bit Overflow Protection
–
Bit-Field Extract, Set, Clear
–
Normalization, Saturation, Bit-Counting
–
Compact 16-Bit Instructions
–
Additional Instructions to Support Complex
Multiplies
C64x+ L1/L2 Memory Architecture
–
32K-Byte L1P Program RAM/Cache (Direct
Mapped)
–
80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
–
64K-Byte L2 Unified Mapped RAM/Cache
(Flexible RAM/Cache Allocation)
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
ARM926EJ-S Core
–
Support for 32-Bit and 16-Bit (Thumb
Mode) Instruction Sets
–
DSP Instruction Extensions and Single
Cycle MAC
–
ARM Jazelle Technology
–
EmbeddedICE-RT Logic for Real-Time
Debug
ARM9 Memory Architecture
–
16K-Byte Instruction Cache
–
8K-Byte Data Cache
–
16K-Byte RAM
–
8K-Byte ROM
Emulation Trace Buffer (ETB11) With 4-KB
Memory for ARM9 Debug
Endianness: Little Endian for ARM and DSP
Video Processing Subsystem
–
Resize Engine Provides:
Resize Images From 1/4x to 4x
Separate Horizontal and Vertical Control
–
Back End Provides:
Hardware On-Screen Display (OSD)
4 - 54 MHz DACs for a Combination of
Composite NTSC/PAL Video
Luma/Chroma Separate Video
(S-video)
Component (YPbPr or RGB) Video
(Progressive)
Digital Output
8-/16-Bit YUV or up to 24-Bit RGB
HD Resolution
Up to 2 Video Windows
External Memory Interfaces (EMIFs)
–
32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
–
Asynchronous16-Bit Wide EMIF (EMIFA)
With 128M-Byte Address Reach
Flash Memory Interfaces
NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
Flash Card Interfaces
–
Multimedia Card (MMC)/Secure Digital (SD)
with Secure Data I/O (SDIO)
–
Compact Flash Controller With True IDE
Mode
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