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P
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 2-19. VPFE Terminal Functions (continued)
SIGNAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
This pin is multiplexed between the VPFE(CCDC) and GPIO.
This pin is CCDC input YI4 and it supports several modes:
In 16-bit CCD Raw mode, it is input CCD4.
In 16-bit YCbCr mode, it is input Y4.
(4)
In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and
CR4 of the lower 8-bit channel.
(4)
This pin is multiplexed between the VPFE (CCDC) and GPIO.
YI4(CCD4)/
GP[40]
IPD
DV
DD33
D14
C18
I/O/Z
This pin is CCDC input YI3 and it supports several modes:
In 16-bit CCD Raw mode, it is input CCD3.
In 16-bit YCbCr mode, it is input Y3.
(4)
In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and
CR3 of the lower 8-bit channel.
(4)
This pin is multiplexed between the VPFE (CCDC) and GPIO.
YI3(CCD3)/
GP[39]
IPD
DV
DD33
B14
A16
I/O/Z
This pin is CCDC input YI2 and it supports several modes:
In 16-bit CCD Raw mode, it is input CCD2.
In 16-bit YCbCr mode, it is input Y2.
(4)
In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and
CR2 of the lower 8-bit channel.
(4)
This pin is multiplexed between the VPFE (CCDC) and GPIO.
YI2(CCD2)/
GP[38]
IPD
DV
DD33
C14
B17
I/O/Z
This pin is CCDC input YI1 and it supports several modes:
In 16-bit CCD Raw mode, it is input CCD1.
In 16-bit YCbCr mode, it is input Y1.
(4)
In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and
CR1 of the lower 8-bit channel.
(4)
This pin is multiplexed between the VPFE (CCDC) and GPIO.
YI1(CCD1)/
GP[37]
IPD
DV
DD33
B15
B18
I/O/Z
This pin is CCDC input YI0 and it supports several modes:
In 16-bit CCD Raw mode, it is input CCD0.
In 16-bit YCbCr mode, it is input Y0.
(4)
In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and
CR0 of the lower 8-bit channel.
(4)
This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.
In VPFE mode, it is the CCD Controller write enable input C_WE.
This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.
In VPFE mode, it is CCDC field identification bidirectional signal
C_FIELD.
YI0(CCD0)/
GP[36]
IPD
DV
DD3
C15
B19
I/O/Z
C_WE/EM_R/W/
GP[35]
IPD
DV
DD33
D13
C17
I/O/Z
C_FIELD/EM_A[21]/
GP[34]
IPD
DV
DD33
D12
C16
I/O/Z
Device Overview
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