參數(shù)資料
型號(hào)： TMSC6701
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FLOATING POINT DIGITAL SIGNAL PROCESSOR
中文描述： 浮點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 9/64頁
文件大小： 862K
代理商： TMSC6701
SPRS067E – MAY 1998 – REVISED MAY 2000
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Signal Descriptions
SIGNAL
TYPE
DESCRIPTION
NAME
NO.
CLOCK/PLL
CLKIN
C10
I
Clock Input
CLKOUT1
AF22
O
Clock output at full device speed
CLKOUT2
AF20
O
Clock output at half of device speed
CLKMODE1
C6
I
Clock mode select
Selects whether the output clock frequency = input clock frequency x4 or x1
CLKMODE0
C5
PLLFREQ3
A9
PLL frequency range (3, 2, and 1)
The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins.
(3 2
PLLFREQ2
D11
I
PLLFREQ1
PLLV
PLLG
B10
D12
A§
A§
A§
PLL analog VCC connection for the low-pass filter
PLL analog GND connection for the low-pass filter
C12
PLLF
A11
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS
L3
I
JTAG test-port mode select (features an internal pullup)
TDO
W2
O/Z
JTAG test-port data out
TDI
R4
I
JTAG test-port data in (features an internal pullup)
TCK
R3
I
JTAG test-port clock
TRST
T1
I
JTAG test-port reset (features an internal pulldown)
Emulation pin 1, pullup with a dedicated 20-k
resistor
Emulation pin 0, pullup with a dedicated 20-k
resistor
CONTROL
EMU1
Y1
I/O/Z
EMU0
W3
I/O/Z
RESET
K2
I
Device reset
NMI
L2
I
Nonmaskable interrupt
Edge-driven (rising edge)
EXT_INT7
U3
EXT_INT6
V2
I
External interrupts
External interru ts
Edge-driven (rising edge)
EXT_INT5
W1
EXT_INT4
U4
g )
IACK
Y2
O
Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
AA1
INUM2
W4
O
Active interrupt identification number
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt-service fetch-packet ordering
Encoding order follows the interru t-service fetch- acket ordering
INUM1
AA2
INUM0
AB1
LENDIAN
H3
I
If high, LENDIAN selects little-endian byte/half-word addressing order within a word
If low, LENDIAN selects big-endian addressing
PD
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these
pins.
§A = Analog Signal (PLL Filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k
resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-k
resistor.
D3
O
Power-down mode 3 (active if high)
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