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參數(shù)資料
| 型號： | TMSC6701 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FLOATING POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 浮點數(shù)字信號處理器 |
| 文件頁數(shù)： | 50/64頁 |
| 文件大?。?/td> | 862K |
| 代理商： | TMSC6701 |
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SPRS067E – MAY 1998 – REVISED MAY 2000
50
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics for McBSP
(see Figure 31)
NO.
PARAMETER
’C6701-120
’C6701-150
’C6701-167
UNIT
MIN
MAX
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
3
15
ns
2
tc(CKRX)
tw(CKRX)
td(CKRH-FRV)
Cycle time, CLKR/X
CLKR/X int
2P§
C – 1#
ns
3
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
C + 1#
ns
4
Delay time, CLKR high to internal FSR valid
CLKR int
–4
4
ns
9
td(CKXH-FXV)
Delay time CLKX high to internal FSX valid
Delay time, CLKX high to internal FSX valid
CLKX int
–4
5
ns
CLKX ext
3
16
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
Disable time, DX high im edance following last data bit from
CLKX high
CLKX int
–3
2
ns
CLKX ext
2
9
13
td(CKXH-DXV)
Delay time CLKX high to DX valid
Delay time, CLKX high to DX valid.
CLKX int
–2
4
ns
CLKX ext
3
16
14
td(FXH-DXV)
Delay time, FSX high to DX valid.
ONLY applies when in data delay 0 (XDATDLY = 00b) mode.
FSX int
FSX ext
–2
2
4
ns
10
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
§P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz),
whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting
the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum
CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the
McBSP communicates to is a slave.
#C =
H or L
S =
sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 50 MHz limit.
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