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參數(shù)資料
| 型號： | TMSC6701 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FLOATING POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 浮點數(shù)字信號處理器 |
| 文件頁數(shù)： | 24/64頁 |
| 文件大?。?/td> | 862K |
| 代理商： | TMSC6701 |
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SPRS067E – MAY 1998 – REVISED MAY 2000
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clock PLL
All of the internal ’C67x clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3,
Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.
Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the ’C67x device and the external
clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise
and fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section.
Table 3. CLKOUT1 Frequency Ranges
PLLFREQ3
(A9)
0
0
0
Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain
the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example,
for CLKOUT1 = 133 MHz, choose PLLFREQ value of 000b. For CLKOUT1 = 167 MHz, choose PLLFREQ value
of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved.
PLLFREQ2
(D11)
0
0
1
PLLFREQ1
(B10)
0
1
0
CLKOUT1 Frequency Range
(MHz)
50–140
65–167
130–167
Table 4. ’C6701 PLL Component Selection Table
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
50–167
CLKOUT2
RANGE
(MHz)
R1
(
)
C1
(nF)
C2
(pF)
TYPICAL
LOCK TIME
(
μ
s)
x4
12.5–41.7
25–83.5
60.4
27
560
75
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100
μ
s, the maximum value may be as long as 250
μ
s.
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