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參數(shù)資料
| 型號： | TMSC6701 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FLOATING POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 浮點數(shù)字信號處理器 |
| 文件頁數(shù)： | 46/64頁 |
| 文件大小： | 862K |
| 代理商： | TMSC6701 |
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SPRS067E – MAY 1998 – REVISED MAY 2000
46
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles
(see Figure 27, Figure 28, Figure 29, and
Figure 30)
NO.
’C6701-120
’C6701-150
’C6701-167
UNIT
MIN
MAX
1
tsu(SEL-HSTBL)
th(HSTBL-SEL)
tw(HSTBL)
tw(HSTBH)
tsu(SEL-HASL)
th(HASL-SEL)
tsu(HDV-HSTBH)
th(HSTBH-HDV)
Setup time, select signals§ valid before HSTROBE low
Hold time, select signals§ valid after HSTROBE low
4
ns
2
2
ns
3
Pulse duration, HSTROBE low
2P
ns
4
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals§ valid before HAS low
Hold time, select signals§ valid after HAS low
2P
ns
10
4
ns
11
2
ns
12
Setup time, host data valid before HSTROBE high
3
ns
13
Hold time, host data valid after HSTROBE high
2
ns
14
th(HRDYL-HSTBL)
Hold time, HSTROBE low after HRDY low. HSTROBE should not be inacti-
vated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
1
ns
18
tsu(HASL-HSTBL)
th(HSTBL-HASL)
Setup time, HAS low before HSTROBE low
2
ns
19
Hold time, HAS low after HSTROBE low
2
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
§Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
switching characteristics during host-port interface cycles
(see Figure 27, Figure 28, Figure 29,
and Figure 30)
NO.
PARAMETER
’C6701-120
’C6701-150
’C6701-167
UNIT
MIN
MAX
5
td(HCS-HRDY)
td(HSTBL-HRDYH)
td(HSTBL-HDLZ)
td(HDV-HRDYL)
toh(HSTBH-HDV)
td(HSTBH-HDHZ)
td(HSTBL-HDV)
td(HSTBH-HRDYH)
td(HASL-HRDYH)
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
#This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.
||This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
Delay time, HCS to HRDY
Delay time, HSTROBE low to HRDY high#
1
12
ns
6
1
12
ns
7
Delay time, HSTROBE low to HD low impedance for an HPI read
4
ns
8
Delay time, HD valid to HRDY low
P – 3
P + 3
ns
9
Output hold time, HD valid after HSTROBE high
3
12
ns
15
Delay time, HSTROBE high to HD high impedance
3
12
ns
16
Delay time, HSTROBE low to HD valid
Delay time, HSTROBE high to HRDY high||
3
12
ns
17
1
12
ns
20
Delay time, HAS low to HRDY high
3
12
ns
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