參數(shù)資料
型號: TMSC6701
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FLOATING POINT DIGITAL SIGNAL PROCESSOR
中文描述: 浮點數(shù)字信號處理器
文件頁數(shù): 45/64頁
文件大小: 862K
代理商: TMSC6701
SPRS067E – MAY 1998 – REVISED MAY 2000
45
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles
(see Figure 26)
NO.
’C6701-120
’C6701-150
’C6701-167
UNIT
MIN
MAX
2
tw(ILOW)
tw(IHIGH)
Width of the interrupt pulse low
2P
ns
3
Width of the interrupt pulse high
2P
ns
Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can
be connected to asynchronous inputs.
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
switching characteristics during interrupt response cycles
§
(see Figure 26)
NO.
PARAMETER
’C6701-120
’C6701-150
’C6701-167
UNIT
MIN
MAX
1
tR(EINTH-IACKH)
td(CKO2L-IACKV)
td(CKO2L-INUMV)
td(CKO2L-INUMIV)
§P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2
×
CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
Response time, EXT_INTx high to IACK high
9P
ns
4
Delay time, CLKOUT2 low to IACK valid
–0.5P
13 – 0.5P
ns
5
Delay time, CLKOUT2 low to INUMx valid
10 – 0.5P
ns
6
Delay time, CLKOUT2 low to INUMx invalid
–0.5P
ns
Interrupt Number
6
5
4
4
3
2
CLKOUT2
EXT_INTx, NMI
1
Intr Flag
IACK
INUMx
Figure 26. Interrupt Timing
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