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參數(shù)資料
| 型號(hào)： | TMS44409P |
| 廠(chǎng)商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| 中文描述： | 1048576字4位動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 8/26頁(yè) |
| 文件大小： | 413K |
| 代理商： | TMS44409P |
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TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’44409-60
’44409P-60
’44409-70
’44409P-70
’44409-80
’44409P-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tRC
tRWC
tPRWC
tRASP
tRAS
tRP
tWP
tASC
tASR
tDS
tRCS
tCWL
tRWL
tWCS
tWSR
tCAH
tDH
tRAH
tRCH
tRRH
tWCH
tWHR
tROH
tAWD
tCHR
tCRP
tCSR
tCWD
tOEH
tOED
tRAD
tRAL
tCAL
tRCD
tRPC
NOTES:
Cycle time, random read or write (see Note 7)
110
130
150
ns
Cycle time, read-write (see Note 7)
150
175
200
ns
Cycle time, EDO page-mode read-write
80
90
100
ns
Pulse duration, page mode, RAS low, (see Note 8)
60
100 000
70
100 000
80
100 000
ns
Pulse duration, nonpage mode, RAS low, (see Note 8)
60
10 000
70
10 000
80
10 000
ns
Pulse duration, RAS high (precharge)
40
50
60
ns
Pulse duration, W
10
10
10
ns
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
Setup time, data before W low (see Note 9)
0
0
0
ns
Setup time, read before CAS low
0
0
0
ns
Setup time, W low before CAS high
10
12
15
ns
10
12
15
ns
Setup time, W low before CAS low (early-write operation only)
0
0
0
ns
Setup time, W high (CBR refresh only)
10
10
10
ns
Hold time, column address after CAS low
10
15
15
ns
Hold time, data after CAS low (see Note 9)
10
15
15
ns
Hold time, row address after RAS low
10
10
10
ns
Hold time, read after CAS high (see Note 10)
0
0
0
ns
Hold time, read after RAS high (see Note 10)
0
0
0
ns
Hold time, write after CAS low (early-write operation only)
10
15
15
ns
Hold time, W high (CBR refresh only)
10
10
10
ns
Hold time, RAS referenced to OE
10
10
10
ns
Delay time, column address to W low (read-write operation only)
55
63
70
ns
Delay time, RAS low to CAS high (CBR refresh only)
15
15
20
ns
Delay time, CAS high to RAS low
0
0
0
ns
Delay time, CAS low to RAS low (CBR refresh only)
5
5
5
ns
Delay time, CAS low to W low (read-write operation only)
40
46
50
ns
Hold time, OE command
15
18
20
ns
Delay time, valid data in after OE high
15
18
20
ns
Delay time, RAS low to column address
15
30
15
35
15
40
ns
Delay time, column address to RAS high
30
35
40
ns
Delay time, column address to CAS high
20
25
30
ns
Delay time, RAS low to CAS low (see Note 11)
20
45
20
52
20
60
ns
Delay time, RAS high to CAS low (CBR refresh only)
0
0
0
ns
7. All timing requirements assume tT = 5 ns.
8. In a read-write cycle, tRWD and tRWL must be observed.
9. Referenced to the later of CAS or W in write operations
10. The minimum value is measured when tRCD is set to tRCD min as a reference.
11. The minimum value is specified only to assure access time.
A
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