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參數(shù)資料
| 型號： | TMS44409P |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| 中文描述： | 1048576字4位動態(tài)隨機存取存儲器 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 413K |
| 代理商： | TMS44409P |
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The data input is disabled when the read mode is selected.
When W goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle,
permitting a write operation independent of the state of OE. This permits early-write operation to be completed
with OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is
high (see Figure 8).
data in/data out (DQ1–DQ4)
Data is written during a write or a read-modify-write cycle. Depending on the mode of operation, data is strobed
in by the later falling edge of CAS or W with setup and hold times referenced to the latter edge. The DQs drive
valid data after all access times are met and remain valid except in the cases described in the W and OE
descriptions (above).
refresh
A refresh operation must be performed at least once every 16 ms to retain data. This is achieved by strobing
each of the 1 024 rows (A0–A9). A normal read or write cycle refreshes all bits in each row that is selected. A
RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished
by holding CAS at V
IL
after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle. The external address is ignored during the hidden-refresh cycle.
CAS-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter t
CSR
) and holding it low after RAS
falls (see parameter t
CHR
). For successive CBR-refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally.
self-refresh (TMS44409P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100
μ
s. The chip is then refreshed by an on-board oscillator. No external address is required
because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS
are brought high to satisfy t
CHS
. Upon exiting the self-refresh mode, a burst refresh (refresh of a full set of row
addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully
refreshed.
power up
To achieve proper device operation, an initial pause of 200
μ
s followed by a minimum of eight initialization cycles
is required after power up to the full V
CC
level is achieved. These eight initialization cycles need to include at
least one refresh (RAS only or CBR) cycle.
test mode
A design for test (DFT) mode is incorporated in the TMS44409. A CBR with W low (WCBR) cycle is used to enter
the test mode. In the test mode, data is written into and read from eight sections of the array in parallel. All data
is written into the array through DQ1. Data is compared upon reading and if all bits are equal, all DQ pins go
high. If any one bit is different, a DQ pin goes low. Any combination of read, write, read-write, or page-mode
can be used in the test mode. The test-mode function reduces test times by enabling the 1-megabit
×
4 DRAM
to be tested as if it were a 512K DRAM where column address 0 is not used. A RAS-only or CBR-refresh cycle
is used to exit the DFT mode.
A
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