- 您現(xiàn)在的位置：買賣IC網 > PDF目錄385002 > TMS44409P (Texas Instruments, Inc.) 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY PDF資料下載
參數(shù)資料
| 型號： | TMS44409P |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| 中文描述： | 1048576字4位動態(tài)隨機存取存儲器 |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 413K |
| 代理商： | TMS44409P |
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
functional block diagram
4
A0
A1
A9
16
2
10
10
16
16
2
4
Timing and Control
Column-
Address
Buffers
Row-
Address
Buffers
I/O
Buffers
4 of 16
Selection
Column Decode
Sense Amplifiers
R
o
w
D
e
c
o
d
e
16
128K Array
128K Array
128K Array
128K Array
128K Array
128K Array
DQ1–DQ4
RAS
CAS
W
OE
Data-
In
Reg.
Data-
Out
Reg.
8
operation
extended data out
Extended data out allows for data output rates of up to 40 MHz for 60-ns devices. When keeping the same row
address while selecting random column addresses, the time for row-address setup and hold and address
multiplex is eliminated. The maximum number of columns that can be accessed is determined by t
RASP
, the
maximum RAS low time.
Extended data out does not place the DQs into the high-impedance state with the rising edge of CAS. The output
remains valid for the system to latch the data. After CAS goes high, the DRAM decodes the next address. OE
and W can be used to control the output impedance. Descriptions of OE and W further explain EDO operation
benefit.
address (A0–A9)
Twenty address bits are required to decode one of 1048576 storage cell locations. Ten row-address bits are
set up on A0 through A9 and latched onto the chip by the row-address strobe (RAS). The ten column-address
bits are set up on pins A0 through A9 and latched onto the chip by the column-address strobe (CAS). All
addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip-enable in
that it activates the sense amplifiers as well as the row decoder.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 7). There are two
methods for placing the DQs into the high-impedance state and keeping them that way during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for t
CHO
past the CAS
transition. This disables the DQs and they remain disabled, regardless of OE, until CAS falls again. The second
method is to have OE low as CAS transitions high. Then OE can pulse high for a minimum of t
OEP
anytime during
CAS high time, thus, disabling the DQs regardless of further transitions on OE until CAS falls again (see
Figure 7).
A
相關PDF資料 |
PDF描述 |
|---|---|
| TMS45160P | 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS46100 | 4194304-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS46100P | 4194304-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS44100P | 4194304-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS46400 | 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS44460-70DJ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMS44460-70DR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMS4461 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:GRAPHICS SYSTEM PROCESSOR |
| TMS446112SDL | 制造商:TI 功能描述:4461-12 TI SB-174I |
| TMS4461-12SDL | 制造商:TI 功能描述:4461-12 TI SB-174I |
發(fā)布緊急采購，3分鐘左右您將得到回復。