參數(shù)資料
型號(hào): TMC2255
廠商: Fairchild Semiconductor Corporation
英文描述: 8 x 8 Bits, 12 MHz Data Rate CMOS 3 x 3, 5 x 5 Image Convolver(8 x 8位,12 MHz CMOS 3 x 3, 5 x 5 圖像旋轉(zhuǎn)處理機(jī))
中文描述: 8 × 8位,12MHz的數(shù)據(jù)速率的CMOS 3 × 3,5 × 5圖像卷積器(8 × 8位,12兆赫的CMOS 3 × 3,5 × 5圖像旋轉(zhuǎn)處理機(jī))
文件頁(yè)數(shù): 7/20頁(yè)
文件大?。?/td> 124K
代理商: TMC2255
PRODUCT SPECIFICATION
TMC2255
7
Pin Assignments
Pin Descriptions
Pin Name
Inputs
CLK
Pin Number
Pin Function Description
8
Master chip clock, 0 to 30MHz.
of CLK.
Data inputs.
Of the device's five 8-bit data input ports, A, B, and C are used
exclusively as data inputs, whereas D and E are also used to program the device
(see description of CLE pin). For 5x5 convolution, all five ports accept incoming
data. In the other modes, only ports A-C accept incoming data, leaving D and E
dedicated to control and coefficient values, which may be updated at any time. In
all modes, data are loaded on every third rising edge for which CLE makes a
0-to-1 transition. Bits A
7
, B
7
,… are the two's complement sign bits or most
significant unsigned bitsl bits A
0
, B
0
,… are the least significant bits (LSBs).
Active-LOW coefficient and control load enable.
becomes the input port for the coefficients, and D becomes the coefficient write
address and control port. When CLE is HIGH, all coefficients are held unchanged.
A LOW-to-HIGH transition at CLE also synchronizes the TMC2255, ushering in a
new data input.
Coefficient read address.
The chip can hold four "pages" of nine coefficients
each. These two pins determine which of the four coefficient sets is to be used
with the data entering during that cycle.
All operations are referenced to the rising edges
A
C
E
0-7
0-7
0-7
, B
, D
0-7
0-7
,
,
5-3, 68-64;
61-54; 51-44;
43-36; 34-27
CLE
6
When CLE is LOW, E
CRA
1-0
62-63
The timing of coefficient selection by CRA is mode dependent. In the 3 (3x1)
mode, CRA influences all coefficients simultaneously. In the 3x3 and 5x5
convolution modes, however, CRA selects the coefficients for each multiplier
column individually, i.e. three per clock cycle from left to right (see Figure 3). CRA
should be changed only on "data input" clock cycles to avoid corrupting 3x3 or
3 (3x1) work in progress. CRA should not be updated during a 5x5 operation
whose result is needed.
When updating coefficients on-the-fly, the user should not set CRA
the same page, but should read from one page while writing to another.
1-0
and D
5-4
to
1
2
3
4
5
65-2255-06
1 68
Pin
6
7
8
9
10
11
12
13
14
15
16
17
GND
V
DD
A
2
A
1
A
0
Name
CLE
OE
CLK
GND
V
DD
Z
11
Z
10
GND
Z
9
Z
8
Z
7
V
DD
18
19
20
21
22
Pin
23
24
25
26
27
28
29
30
31
32
33
34
GND
Z
6
Z
5
Z
4
Z
3
Name
Z
2
Z
1
Z
0
GND
E
7
E
6
E
5
E
4
E
3
E
2
E
1
E
0
35
36
37
38
39
Pin
40
41
42
43
44
45
46
47
48
49
50
51
GND
D
7
D
6
D
5
D
4
Name
D
3
D
2
D
1
D
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
52
53
54
55
56
Pin
57
58
59
60
61
62
63
64
65
66
67
68
GND
V
DD
B
7
B
6
B
5
Name
B
4
B
3
B
2
B
1
B
0
CRA
1
CRA
0
A
7
A
6
A
5
A
4
A
3
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