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參數資料
| 型號： | TMC2255 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8 x 8 Bits, 12 MHz Data Rate CMOS 3 x 3, 5 x 5 Image Convolver(8 x 8位,12 MHz CMOS 3 x 3, 5 x 5 圖像旋轉處理機) |
| 中文描述： | 8 × 8位，12MHz的數據速率的CMOS 3 × 3，5 × 5圖像卷積器（8 × 8位，12兆赫的CMOS 3 × 3，5 × 5圖像旋轉處理機） |
| 文件頁數： | 12/20頁 |
| 文件大?。?/td> | 124K |
| 代理商： | TMC2255 |
TMC2255
PRODUCT SPECIFICATION
12
In Figure 6, CLK rising edges at t = 3, 6, 9, … again resyn-
chronize the chip, but configuration and coefficients my be
changed twice as often, at t = 1, 2, 4, 5, 7, 8, … .
In Figure 7, data timing is the sames as that of Figure 4.
However, since CLE is left LOW after the one-cycle initial-
ization pulse, instructions and coefficients may be updates on
every clock cycle, or three times per data input. Instructions
entering between data values, e.g. at t = 4 or t = 5, affect the
next data value (i.e., that entering at t = 6). Instructions enter-
ing with a given data value (e.g., t = 6) affect the next data
input (i.e., at t = 9).
Figure 6. 3xX Modes, Periodic Short CLE Pulses
Figure 7. 3xX Modes, Single CLE Rising Edge
CLK
OE
CLE
A
7-0
B
7-0
C
7-0
D
7-0
E
7-0
Z
11-0
(3 x 1)
L
3
6
9
12
15
18
L1
L2
L3
M1
L1
L2+M1
M2
M3
L
L
L
L
M
M
M
M
N
N
N
N
P
P
P
P
Q
Q
Q
Q
M
N
P
Q
(3 x 3)
Z
11-0
65-2255-09
CLK
OE
CLE
A
7-0
B
7-0
C
7-0
D
7-0
E
7-0
Z
11-0
(3 x 1)
L
3
6
9
12
15
18
K
L1
L2
L3
M1
L1
L2+M1
M2
M3
K
L
L
L
L
M
M
M
M
N
N
N
N
P
P
P
P
Q
Q
Q
Q
M
N
P
Q
(3 x 3)
Z
11-0
65-2255-10
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