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參數(shù)資料
| 型號： | TMC2255 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8 x 8 Bits, 12 MHz Data Rate CMOS 3 x 3, 5 x 5 Image Convolver(8 x 8位,12 MHz CMOS 3 x 3, 5 x 5 圖像旋轉(zhuǎn)處理機) |
| 中文描述： | 8 × 8位，12MHz的數(shù)據(jù)速率的CMOS 3 × 3，5 × 5圖像卷積器（8 × 8位，12兆赫的CMOS 3 × 3，5 × 5圖像旋轉(zhuǎn)處理機） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 124K |
| 代理商： | TMC2255 |
TMC2255
PRODUCT SPECIFICATION
14
In 5x5 mode, CLE should not be left LOW continuously,
since ports D and E must serve as data inputs on every third
clock cycle. If CLE is LOW on a data input cycle, the chip
will interpret the current D and E inputs as both data and
instructions/coefficients.
Figure 11. I/O Timing Diagram
Power-Up Sequence
To ensure proper operation, the TMC2255 should receive at
least two clock rising edges soon after power-up, with CLE
making a 0-to-1 transition on edge 4, 5, or 6. Otherwise,
some of the internal multiplexers will power up in disal-
lowed states and draw excessive power.
Data Formats
Figure 12 summarizes the TMC2255’s data and coefficient
formats for all operating modes. Although integer weighting
of input data is shown, the binary point may be moved any-
where to the left, as long as the binary point of the output is
moved the same distance. Likewise, the coefficient binary
point can be moved, as long as the output binary point is
moved equally or the data input binary point is moved in the
opposite direction. In all coefficients and in all two’s
complement data, the most significant bit carries a negative
weighting.
t
CY
1
2
3
4
5
t
PWH
t
PWL
65-2255-14
t
D
t
HO
t
H
t
S
CLK
A, B, C, D, E
CRA, CLE
Z
PREVIOUS
NEW
Figure 10. 5x5 Convolution, Periodic Short CLE Pulse
CLK
OE
CLE
A
7-0
B
7-0
C
7-0
D
7-0
E
7-0
Z
11-0
L
3
6
9
12
15
18
KC
L1
L2+M1
KC
L
L
LC
LC
LC
LC
M
M
MC
MC
MC
MC
NC
NC
NC
NC
PC
PC
PC
PC
QC
QC
QC
QC
N
N
P
P
Q
Q
M
N
P
Q
65-2255-13
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