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參數(shù)資料
| 型號： | TMC2255 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8 x 8 Bits, 12 MHz Data Rate CMOS 3 x 3, 5 x 5 Image Convolver(8 x 8位,12 MHz CMOS 3 x 3, 5 x 5 圖像旋轉(zhuǎn)處理機) |
| 中文描述： | 8 × 8位，12MHz的數(shù)據(jù)速率的CMOS 3 × 3，5 × 5圖像卷積器（8 × 8位，12兆赫的CMOS 3 × 3，5 × 5圖像旋轉(zhuǎn)處理機） |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 124K |
| 代理商： | TMC2255 |
PRODUCT SPECIFICATION
TMC2255
13
In Figure 8, the CLK rising edge at t = 3 synchronizes the
operation. The final configuration and coefficient values are
loaded through ports D and E at t = 2, and the first incoming
data enter ports A through E at t = 6. The first results using
the t = 6 input appears after t = 15 and remains until t = 18.
The last result using the t = 6 input emerge after t = 27 and
remains until t = 30. The part operates continuously, with
data inputs read on every third rising edge of CLK and a new
output available t
DO
after every third rising edge of CLK.
In Figure 9, one new coefficient or configuration value can
be input for every data input, at t = 5, 8, 11, … .
In Figure 10, two new coefficients or configuration values
can be loaded for every incoming data point, at t = 4, 5, 7, 8,
10, 11, … .
Figure 8. 5x5 Convolution, Single CLE Rising Edge
Figure 9. 5x5 Convolution, Periodic Long CLE Pulse
CLK
OE
CLE
A
7-0
B
7-0
C
7-0
D
7-0
E
7-0
Z
11-0
L
3
6
9
12
15
18
KC
L1
L2+M1
KC
L
L
M
M
N
N
P
P
Q
Q
M
N
P
Q
65-2255-11
CLK
OE
CLE
A
7-0
B
7-0
C
7-0
D
7-0
E
7-0
Z
11-0
L
3
6
9
12
15
18
KC
L1
L2+M1
KC
L
L
LC
LC
M
M
MC
MC
NC
NC
PC
PC
QC
QC
N
N
P
P
Q
Q
M
N
P
Q
65-2255-12
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