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參數(shù)資料
| 型號： | TMC2255 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8 x 8 Bits, 12 MHz Data Rate CMOS 3 x 3, 5 x 5 Image Convolver(8 x 8位,12 MHz CMOS 3 x 3, 5 x 5 圖像旋轉(zhuǎn)處理機(jī)) |
| 中文描述： | 8 × 8位，12MHz的數(shù)據(jù)速率的CMOS 3 × 3，5 × 5圖像卷積器（8 × 8位，12兆赫的CMOS 3 × 3，5 × 5圖像旋轉(zhuǎn)處理機(jī)） |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 124K |
| 代理商： | TMC2255 |
PRODUCT SPECIFICATION
TMC2255
3
every third clock cycle, the coefficient page to be read and
used in the immediate 3-cycle computation set is selected by
CRA
0
and CRA
1
. Of the nine coefficients per page, K1,i (i =
1 to 3) process the port A (and E) data; K2,i, the port B and
(D) data; and K3,i, the port C data.
Multiplication and Accumulation
The device computes nine products during every three clock
cycles, accumulating them internally to full precision.
Rounding
Accumulated sums of products are rounded before the last 5
or 6 bits are truncated. Rounding is performed by adding
"010000" or "100000" to the emerging data stream, accord-
ing to the desired precision of the output results. When CLE
= 0 and D = 0XXX1111, pin E
position, viz: E
6
= 0: add .010000 and use Z
cant bit; E
6
= 1: add .100000 and use Z
bit, ignoring Z
0
.
6
sets the chip's rounding
0
1
as least significant
as least signifi-
Output Limiting
The device provides programmable output limiting in
unsigned (UN) and/or two's complement (TC) format and for
8, 9, or 12 bits of output precision (including Z
mode, for an RGB-to-YIQ transformation, the device can
limit Z
1
(Y) to 9 bits unsigned while limiting Z
(Q) to 9 bits two's complement.
0
). In 3 (3x1)
3
(I) and Z
3
Outputs
Output is through the 12-bit Z port, which provides 1/2 or 1
LSB precision, relative to the input format. In the 3 (3x1)
mode, three outputs will appear consecutively at the Z port
during each triple clock cycle; for data input on clock rising
edge 0, these results will emerge t
7, 8, and 9. In both convolution modes the results are output
at 1/3 the device master clock rate, with the first point of the
impulse response emerging after clock rising edge 9. To
facilitate connection to a bus, the output buffers are enabled
and disabled (placed in high-impedance state) by asynchro-
nous control OE.
DO
after clock rising edges
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