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參數(shù)資料
| 型號： | TMC2255 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8 x 8 Bits, 12 MHz Data Rate CMOS 3 x 3, 5 x 5 Image Convolver(8 x 8位,12 MHz CMOS 3 x 3, 5 x 5 圖像旋轉(zhuǎn)處理機(jī)) |
| 中文描述： | 8 × 8位，12MHz的數(shù)據(jù)速率的CMOS 3 × 3，5 × 5圖像卷積器（8 × 8位，12兆赫的CMOS 3 × 3，5 × 5圖像旋轉(zhuǎn)處理機(jī)） |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 124K |
| 代理商： | TMC2255 |
TMC2255
PRODUCT SPECIFICATION
2
Structural Block Diagram
MPY-ACC
LIMITER
4x9x8
COEFFICIENT
RAM
A
7-0
8
A
D
20
15
RND
OE
LMT
CLK
CLK/3
CLK
CLK/3
12
12
INPUT
PREADDITION
ROUNDING
LIMITING
OUTPUT
MULTIPLICATION/
ACCUMULATION
8
8
8
2
2
8
B
7-0
Z
11-0
C
7-0
CLE
CWE
CRA
65-2255-02
CLK
D
7-0
E
7-0
CRA
1-0
CONTROL
Functional Description
The TMC2255 contains an array of multipliers and adders,
four 9x8-bit coefficient "pages" and a global control block,
all of which can be initialized or reconfigured through ports
D and E when CLE is LOW. Device parameters include
matrix coefficient, internal device configuration (mode),
rounding precision, and input/output data formats (two's
complement, unsigned, or mixed). After the control parame-
ters have been loaded, device operation commences with the
next clock rising edge on which CLE returns HIGH.
Depending on the mode selected, three or five data are input
in parallel and proceed through a sequence of operations:
Input, Preaddition, Multiply-Accumulation, Rounding, Lim-
iting, and Output. See Figures 1–3 and the Structural Block
Diagram.
Input Stage
Inputs are supplied to ports A through C in all operating
modes on every third clock cycle, beginning with the clock
rising edge that contains the most recent CLE LOW-to-
HIGH transition. Control and/or coefficient parameters can
be input through ports D and E during any of the three mas-
ter clock cycles that make up each data cycle. In the 5x5 con-
volution mode, data enter the device through ports A–E.
Control and/or coefficients may be updated through ports D
and E on the remaining two cycles of each clock triplet.
Input data formats may be unsigned and/or two's comple-
ment, as identified in the mode select field of port E.
Preaddition
In and only in 5x5 convolution, the horizontal and vertical
symmetry of the coefficient permits nine multipliers to do
the work of 25. To facilitate this, the data input into ports A
and E are pre-added before multiplication, as are the B and D
inputs. See Figure 3, the 5x5 Block Diagram.
Coefficient Memory
The TMC2255 contains enough memory to store four
"pages" of nine 8-bit two's complement coefficients each.
When CLE is LOW, a new coefficient is written through port
E to the page and location address identified on port D. On
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