參數(shù)資料
型號(hào)： TMC2255
廠商： Fairchild Semiconductor Corporation
英文描述： 8 x 8 Bits, 12 MHz Data Rate CMOS 3 x 3, 5 x 5 Image Convolver(8 x 8位,12 MHz CMOS 3 x 3, 5 x 5 圖像旋轉(zhuǎn)處理機(jī))
中文描述： 8 × 8位，12MHz的數(shù)據(jù)速率的CMOS 3 × 3，5 × 5圖像卷積器（8 × 8位，12兆赫的CMOS 3 × 3，5 × 5圖像旋轉(zhuǎn)處理機(jī)）
文件頁(yè)數(shù)： 10/20頁(yè)
文件大?。?/td> 124K
代理商： TMC2255
TMC2255
PRODUCT SPECIFICATION
10
Timing
Result Latency
Device operating mode affects when valid results are avail-
able at the output port Z
11–0
. The three results of a 3x1 triple
dot product whose inputs enter on clock rising edge 0 will be
available t
DO
after clock rising edges 7, 8, and 9. In a 3x3
and 5x5 convolution, the first three impulse response points
will emerge after clock rising edges 9, 12, and 15. The last
two points of a 5-point response (5x5 mode) will follow after
rising edges 18 and 21.
Instructions, Inputs, and Synchronization
Each rising edge of CLK which bears a CLE LOW-to-HIGH
transition resynchronizes the device. If CLE goes from LOW
to HIGH on clock rising edge N, then the chip will resyn-
chronize, starting a new 3-cycle sequence on that edge. It
will look for incoming data at clock rising edges N+3i,
where i = 1, 2, … (see Figures 4 through 10). If CLE is
brought LOW while an operation is already in progress (e.g.,
to update coefficients), it should be brought HIGH only on a
regular data input clock cycle (N+3i), to avoid corrupting
pending results.
IF CLE is LOW, control and/or coefficient information ene-
tering on a rising edge of CLK will affect all subsequent data
inputs until the control parameters are again updated. Inter-
nal pipelining of the controls ensures that “in progress” oper-
ations on data previously input into the device will continue
unaffected, as long as CLE is brought HIGH only on data
input clock edges.
System Timing
Because the TMC2255’s data throughput rate is 1/3 of its
incoming clock rate, the user must synchronize the data
inputs with the chip’s control inputs and internal operation.
Figures 4 through 7 illustrate four ways to use rising edges of
CLE to align data inputs in the 3 (3x1) and 3x3 modes,
whereas Figures 8 through 10 show how to use CLE in the
5x5 mode.
In Figure 4, the CLE 0-to-1 transition on CLK rising edge 3
(t = 3) initialized the chip. The final configuration and coeffi-
cient values are loaded through ports D and E at t = 2 and the
first incoming data enter ports A, B, and C on rising edge 6.
In 3 (3x1) mode, the three results from the t = 6 input data
emerge after t = 13, 14, and 15. In 3x3 mode, the first result
from the edge 6 input data appears after edge 15 and remains
until t = 18, when the second result using t = 6 inputs (which
is the first result using t = 9 inputs) emerges. After t = 18, the
convolution of the t = 6, t = 9, and t = 12 inputs, the last out-
put involving the t = 6 input, appears. The part operates con-
tinuously, with inputs read on every third rising clock edge
and a new output available t
DO
after each rising clock edge
(3 (3x1) mode) or every third rising edge (3x3 mode).
In Figure 5, CLK rising edges at t = 3, 6, 9, … resynchronize
the chip, with configuration or coefficient updates at t = 2, 5,
8, … . Data input/output timing is unchanged from Figure 3.
Table 4. Output Limiting
E
7–0
=
0X000XXX
0X001XXX
0X010XXX
0X011XXX
0X100XXX
0X101XXX
0X110XXX
0X111XXX
1XXXXXXX
Limit Z1 or Z
Limiter disabled
UN9
TC12
UN12
TC9
UN9
Reserved—Do not use
UN8
Unchanged from previous setting
Limit Z2
Limit Z3
Range (RND = 0)
UN9
TC12
UN12
TC9
TC9
UN9
TC12
UN12
TC9
TC9
0, 255.5
-1024, 1023.5
0, 2047.5
-128, 127.5
(Mixed)
UN8
UN8
0, 127.5
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