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參數資料
| 型號： | TMC2255 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8 x 8 Bits, 12 MHz Data Rate CMOS 3 x 3, 5 x 5 Image Convolver(8 x 8位,12 MHz CMOS 3 x 3, 5 x 5 圖像旋轉處理機) |
| 中文描述： | 8 × 8位，12MHz的數據速率的CMOS 3 × 3，5 × 5圖像卷積器（8 × 8位，12兆赫的CMOS 3 × 3，5 × 5圖像旋轉處理機） |
| 文件頁數： | 1/20頁 |
| 文件大小： | 124K |
| 代理商： | TMC2255 |
www.fairchildsemi.com
Features
8-bit data and coefficient input precision
Triple 3x1 matrix-vector multiplication mode
3x3 and 5x5 two-dimensional convolution modes
TTL-compatible I/O with three-state output bus
Offered in 68-contact plastic chip carrier (PLCC)
Built-in 8-, 9-, and 12-bit arithmetic limiter
Two's complement, unsigned, or mixed data formats
Applications
RGB to/from YUV/YIQ color space conversion
3x3 or 5x5 two-dimensional FIR filtering
Edge enhancement and general image processing
Robotics and image recognition
Electronic darkroom
Desktop publishing
Description
Like the faster TMC2250, the low-cost TMC2255 can per-
form a triple 3x1 matrix-vector multiplication or a 3x3 con-
volution. It can also perform a 5x5 convolution with
bidimensionally symmetrical coefficients. The on-chip coef-
ficient memory stores four sets of nine 8-bit two's comple-
ment coefficients. The device accepts unsigned and/or two's
complement data at 1/3 of the applied clock rate.
The 3 (3x1) matrix multiply mode supports various 3-space
numerical operations, such as video standards conversion
(e.g. YIQ to RGB) or three-dimensional perspective transfor-
mation. Three input ports accept the 8-bit two's complement
and/or unsigned magnitude data. The two remaining input
ports can be loaded with coefficients and/or device control
parameters "on-the-fly." In this mode, an output is generated
on every clock cycle.
The 3x3 and 5x5 pixel image convolver modes support
numerous functions, including static filtering and edge
detection. On every third clock cycle, the TMC2255 accepts
three (3x3 mode) or five (5x5 mode) data inputs. In the 5x5
mode, the coefficient kernel must be symmetric both hori-
zontally and vertically. Outputs from the device are gener-
ated on every third clock cycle, matching the input pixel data
rate, and can be limited ("clipped") to 8, 9, or 12 bits.
The TMC2255 will operate at clock rates of 0 to 36 MHz
over the full commercial temperature (0
ply voltage ranges.
°
C to 70
°
C) and sup-
Logic Symbol
DATA
INPUTS
TMC2255
CONTROL
INPUTS
DATA
OUTPUTS
A
7-0
8
8
8
8
8
2
12
65-2255-01
CLE
CRA
1-0
CLK
B
7-0
C
7-0
Z
11-0
OE
D
7-0
E
7-0
T MC2255
CMOS 3 x 3, 5 x 5 Image Convolver
8 x 8 Bits, 12 MHz Data Rate
Rev. 1.0.1
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