參數(shù)資料
型號： TLV320AIC3120IRHBR
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： AUDIO AMPLIFIER, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 9/150頁
文件大?。?/td> 1507K
代理商： TLV320AIC3120IRHBR
SLAS653 – FEBRUARY 2010
www.ti.com
Page 1 / Register 50 (0x32): Input CM Settings
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: MIC1LP input is floating, if it is not used for the MIC PGA and analog bypass.
1: MIC1LP input is connected to CM internally, if it is not used for the MIC PGA and analog bypass.
D6
R/W
0
0: MIC1RP input is floating, if it is not used for the MIC PGA and analog bypass.
1: MIC1RP input is connected to CM internally, if it is not used for the MIC PGA and analog bypass.
D5
R/W
0
0: MIC1LM input is floating, if it is not used for the MIC PGA.
1: MIC1LM input is connected to CM internally, if it is not used for the MIC PGA.
D4–D1
R/W
0000
Reserved. Write only zeros to these bits.
D0
R
0
0: Not all programmed analog gains to the ADC have been applied yet.
1: All programmed analog gains to the ADC have been applied.
Page 1 / Register 51 (0x33) Through Page 1 / Register 127 (0x7F): Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
XXXX XXXX
Reserved. Write only the reset value to these bits.
6.4
Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
Default values shown for this page only become valid 100 ms following a hardware or software reset.
Page 3 / Register 0: Page Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
The only register used in page 3 is register 16. The remaining page-3 registers are reserved and should
not be written to.
Page 3 / Register 16: Timer Clock MCLK Divider
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
1
0: Internal oscillator is used for programmable delay timer.
1: External MCLK(1) is used for programmable delay timer.
D6–D0
R/W
0000 0001
MCLK Divider to Generate 1-MHz Clock for the Programmable Delay Timer
000 0000: MCLK divider = 128
000 0001: MCLK divider = 1
000 0010: MCLK divider = 2
...
111 1110: MCLK divider = 126
111 1111: MCLK divider = 127
(1)
External clock is used only to control the delay programmed between the conversions and not used for doing the actual conversion. This
feature is provided in case a more accurate delay is desired, because the internal oscillator frequency varies from device to device.
6.5
Control Registers, Page 4: ADC Digital Filter Coefficients
Default values shown for this page only become valid 100 ms following a hardware or software reset.
Page 4 / Register 0 (0x00): Page Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
106
REGISTER MAP
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3120
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