參數(shù)資料
型號(hào): TLV320AIC3120IRHBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: AUDIO AMPLIFIER, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù): 64/150頁
文件大?。?/td> 1507K
代理商: TLV320AIC3120IRHBR
SLAS653 – FEBRUARY 2010
www.ti.com
Class-D mono amplifier for 4-
or 8– speakers
Pin-controlled or register-controlled volume level
Power-down de-pop and power-up soft start
Analog inputs
I2C control interface
Power-down control block
Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I2C
interface is used to write to the control registers to configure the device.
The I2C address assigned to the TLV320AIC3120 is 001 1000. This device always operates in an I2C
slave mode. All registers are 8-bit, and all writable registers have read-back capability. The device
auto-increments to support sequential addressing and can be used with I2C fast mode. Once the device is
reset, all appropriate registers are updated by the host processor to configure the device as needed by the
user.
5.2.1
Device Initialization
5.2.1.1
Reset
The TLV320AIC3120 internal logic must be initialized to a known condition for proper device function. To
initialize the device to its default operating condition, the hardware reset pin (RESET) must be pulled low
for at least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up.
It is recommended that while the DVDD supply is being powered up, the RESET pin be pulled low.
The device can also be reset via software reset. Writing a 1 into page 0 / register 1, bit D0 resets the
device.
5.2.1.2
Device Start-Up Lockout Times
After the TLV320AIC3120 is initialized through hardware reset at power-up or software reset, the internal
memories are initialized to default values. This initialization takes place within 1 ms after pulling the
RESET signal high. During this initialization phase, no register-read or register-write operation should be
performed on ADC or DAC coefficient buffers. Also, no block within the codec should be powered up
during the initialization phase.
5.2.1.3
PLL Start-Up
Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up
command of the PLL and before the clocks are available to the codec. This delay is to ensure stable
operation of the PLL and clock-divider logic.
5.2.1.4
Power-Stage Reset
The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has
occurred. Using this reset re-enables the output stage without resetting all of the registers in the device.
Each of the two power stages has its own dedicated reset bit. The headphone power-stage reset is
performed by setting page 1 / register 31, bit D7 for HPOUT. The speaker power-stage reset is performed
by setting page 1 / register 32, bit D7 for SPKP and SPKM.
5.2.1.5
Software Power Down
By default, all circuit blocks are powered down following a reset condition. Hardware power up of each
circuit block can be controlled by writing to the appropriate control register. This approach allows the
lowest power-supply current for the functionality required. However, when a block is powered down, all of
the register settings are maintained as long as power is still being applied to the device.
20
APPLICATION INFORMATION
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3120
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