參數(shù)資料
型號: TLV320AIC3120IRHBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: AUDIO AMPLIFIER, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù): 113/150頁
文件大小: 1507K
代理商: TLV320AIC3120IRHBR
PLL
(R
J.D)/P
PLL_CLKIN
CODEC_CLKIN
ADC_CLK
DAC_MOD_CLK
DAC_CLK
ADC_MOD_CLK
NDAC = 1, 2, ..., 127, 128
MDAC = 1, 2, ..., 127, 128
DOSR = 1, 2, ..., 1023, 1024
AOSR = 1, 2, ..., 1023, 1024
MADC = 1, 2, ..., 127, 128
NADC = 1, 2, ..., 127, 128
MCLK
BCLK
GPIO1
DIN
MCLK
BCLK
GPIO1
PLL_CLK
NADC
MADC
MDAC
DOSR
AOSR
NDAC
To DAC_miniDSP
Clock Generation
To ADC_miniDSP
Clock Generation
DAC_f
S
ADC_f
S
B0357-02
S
CODEC _ CLKIN
ADC _ f
NADC MADC AOSR
=
S
CODEC _ CLKIN
DAC _ f
NDAC MDAC DOSR
=
CODEC _ CLKIN
ADC _ MOD _ CLK
NADC MADC
=
CODEC _ CLKIN
DAC _ MOD _ CLK
NDAC MDAC
=
www.ti.com
SLAS653 – FEBRUARY 2010
highly-flexible clock dividers shown in Figure 5-33 to generate the various clocks required for ADC, DAC
and digital processing sections. In the event that the desired audio or miniDSP clocks cannot be
generated from the reference clocks on MCLK, BCLK, or GPIO1, the TLV320AIC3120 also provides the
option of using the on-chip PLL, which supports a wide range of fractional multiplication values to generate
the required clocks. Starting from CODEC_CLKIN, the TLV320AIC3120 provides several programmable
clock dividers to help achieve a variety of sampling rates for the ADC and DAC.
Figure 5-33. Clock Distribution Tree
(8)
Copyright 2010, Texas Instruments Incorporated
APPLICATION INFORMATION
65
Product Folder Link(s): TLV320AIC3120
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