參數(shù)資料
型號: TLV320AIC3120IRHBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: AUDIO AMPLIFIER, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù): 7/150頁
文件大?。?/td> 1507K
代理商: TLV320AIC3120IRHBR
SLAS653 – FEBRUARY 2010
www.ti.com
Page 1 / Register 42 (0x2A): Class-D Output Driver
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R/W
000
Reserved. Write only zeros to these bits.
D4–D3
R/W
00
00: Class-D driver output stage gain = 6 dB
01: Class-D driver output stage gain = 12 dB
10: Class-D driver output stage gain = 18 dB
11: Class-D driver output stage gain = 24 dB
D2
R/W
0
0: Class-D driver is muted.
1: Class-D driver is not muted.
D1
R/W
0
Reserved. Write only zero to this bit.
D0
R
0
0: Not all programmed gains to class-D driver have been applied yet.
1: All programmed gains to class-D driver have been applied.
Page 1 / Register 43 (0x2B): Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
XXXX XXXX
Reserved. Do not wite to this register.
Page 1 / Register 44 (0x2C): HP Driver Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R/W
001
Debounce time for the headset short-circuit detection
MCLK/DIV (Page 3 /
(1)
register 16) = 1-MHz
Internal Oscillator Source
Source
000: Debounce time =
0 ms
001: Debounce time =
8 ms
7.8 ms
010: Debounce time =
16 ms
15.6 ms
011: Debounce time =
32 ms
31.2 ms
100: Debounce time =
64 ms
62.4 ms
101: Debounce time =
128 ms
124.9 ms
110: Debounce time =
256 ms
250 ms
111: Debounce time =
512 ms
500 ms
Note: These values are based on a nominal oscillator
frequency of 8.2 MHz. Values will scale to the actual
oscillator frequency.
D4–D3
R/W
00
00: Default mode for the DAC
01: DAC performance increased by increasing the current
10: Reserved
11: DAC performance increased further by increasing the current again
D2
R/W
0
0: HPOUT output driver is programmed as headphone driver.
1: HPOUT output driver is programmed as lineout driver.
D1–D0
R/W
00
Reserved. Write only zeros to these bits.
(1)
The clock used for the debounce has a clock period = debounce duration/8.
Page 1 / Register 45 (0x2D): Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
XXXX XXXX
Reserved. Do not write to these registers.
104
REGISTER MAP
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3120
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