參數資料
型號: TLV320AIC3120IRHBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: AUDIO AMPLIFIER, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數: 84/150頁
文件大?。?/td> 1507K
代理商: TLV320AIC3120IRHBR
www.ti.com
SLAS653 – FEBRUARY 2010
Based on the identified filter type and the required signal processing capabilities, the appropriate
processing block can be determined from the list of available processing blocks (PRB_R4 to PRB_R18).
Based on the available master clock, the chosen AOSR and the targeted sampling rate, the clock divider
values NADC and MADC can be determined. If necessary, the internal PLL can add a large degree of
flexibility.
In summary, CODEC_CLKIN (derived directly from the system clock source or from the internal PLL)
divided by MADC, NADC, and AOSR must be equal to the ADC sampling rate ADC_fS. The
CODEC_CLKIN clock signal is shared with the DAC clock-generation block.
CODEC_CLKIN = NADC × MADC × AOSR × ADC_fS
To a large degree, NADC and MADC can be chosen independently in the range of 1 to 128. In general,
NADC should be as large as possible as long as the following condition can still be met:
MADC × AOSR / 32
≥ RC
RC is a function of the chosen processing block and is listed in Table 5-19.
The common-mode voltage setting of the device is determined by the available analog power supply.
At this point, the following device specific parameters are known: PRB_Rx, AOSR, NADC, MADC, input
and output common-mode values. If the PLL is used, the PLL parameters P, J, D, and R are determined
as well.
Step 2
Setting up the device via register programming:
The following list gives a sequence of items that must be executed in the time between powering the
device up and reading data from the device:
1. Define starting point:
(a) Power up applicable external hardware power supplies
(b) Set register page to 0
(c) Initiate SW reset
2. Program clock settings
(a) Program PLL clock dividers P, J, D, and R (if PLL is used)
(b) Power up PLL (if PLL is used)
(c) Program and power up NADC
(d) Program and power up MADC
(e) Program OSR value
(f) Program I2S word length if required (e.g., 20 bits)
(g) Program the processing block to be used
3. Program analog blocks
(a) Set register page to 1
(b) Program MICBIAS if applicable
(c) Program MicPGA
(d) Program routing of inputs/common mode to ADC input
(e) Unmute analog PGAs and set analog gain
Copyright 2010, Texas Instruments Incorporated
APPLICATION INFORMATION
39
Product Folder Link(s): TLV320AIC3120
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