參數(shù)資料
型號: TLV320AIC3120IRHBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: AUDIO AMPLIFIER, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù): 107/150頁
文件大?。?/td> 1507K
代理商: TLV320AIC3120IRHBR
SLAS653 – FEBRUARY 2010
www.ti.com
Electrical Characteristics (continued)
At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 ×
fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO ADC
Microphone Input to ADC, 984-Hz Sine-Wave Input, fS = 48 kHz, AGC = OFF
MIC with R1 = 20 k
(page 1 / register 48 and
Input signal level (0-dB)
0.707
VRMS
register 49, bits D7–D6)
fS = 48 kHz, 0-dB PGA gain, MIC input ac-shorted to
SNR
Signal-to-noise ratio
ground; measured as idle-channel noise,
80
91
dB
A-weighted(1) (2)
fS = 48 kHz, 0-dB PGA gain, MIC input 1 kHz at
Dynamic range
–60-dBFS input applied, referenced to 0.707-Vrms
91
dB
input, A-weighted (1) (2)
fS = 48 kHz, 0-dB PGA gain, MIC input 1 kHz at
Total harmonic distortion +
THD+N
–2-dBFS input applied, referenced to 0.707 Vrms
–85
–70
dB
noise
input
fS = 48 kHz, 0-dB PGA gain, MIC input 1 kHz at
THD
Total harmonic distortion
–2-dBFS input applied, referenced to 0.707 Vrms
–91
dB
input
Input capacitance
MIC input
2
pF
Microphone Bias
Page 1 / register 46, bits D1–D0 = 10
2.25
2.5
2.75
Voltage output
V
Page 1 / register 46, bits D1–D0 = 01
2
At 4-mA load current, page 1 / register 46, bits D1–D0
5
= 10 (MICBIAS = 2.5 V)
Voltage regulation
mV
At 4-mA load current, page 1 / register 46, bits D1–D0
7
= 01 (MICBIAS = 2 V)
Audio ADC Digital Decimation Filter Characteristics
See Section 5.5.4.4 for audio ADC decimation filter characteristics.
DAC HEADPHONE OUTPUT, AC-Coupled Load = 16
(Single-Ended),
Driver Gain = 0 dB, Parasitic Capacitance = 30 pF
Full-scale output voltage (0
Output common-mode setting = 1.65 V
0.707
Vrms
dB)
SNR
Signal-to-noise ratio
Measured as idle-channel noise, A-weighted(1) (2)
80
95
dB
THD
Total harmonic distortion
0-dBFS input
–85
–65
dB
Total harmonic distortion +
THD+N
0-dBFS input
–82
–60
dB
noise
Mute attenuation
87
dB
PSRR
Power-supply rejection ratio(3)
Ripple on HPVDD (3.3 V) = 200 mVp-p at 1 kHz
–62
dB
RL = 32 , THD+N ≤ –60 dB
20
PO
Maximum output power
mW
RL = 16 , THD+N ≤ –60 dB
60
DAC LINEOUT (HP Driver in Lineout Mode)
SNR
Signal-to-noise ratio
Measured as idle-channel noise, A-weighted
95
dB
THD
Total harmonic distortion
0-dBFS input, 0-dB gain
–86
dB
Total harmonic distortion +
THD+N
0-dBFS input, 0-dB gain
–83
dB
noise
(1)
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2)
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3)
DAC to headphone-out PSRR measurement is calculated as PSRR = 20 × log(
ΔVHPOUT / ΔVHPVDD).
6
ELECTRICAL SPECIFICATIONS
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3120
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