參數(shù)資料
型號(hào)： TL16C552AMFN
廠商： Texas Instruments, Inc.
英文描述： DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO
中文描述： 雙異步通信元帶有FIFO
文件頁數(shù)： 30/39頁
文件大小： 545K
代理商： TL16C552AMFN
TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
Bits 5 – 7: MCR5 – MCR7 are permanently cleared.
MCR
7
MCR
6
MCR
5
MCR
4
MCR
3
MCR
2
MCR
1
MCR
0
Modem Control Register
Data Terminal
Ready
Request
to Send
Out 1
(internal)
Out 2
(internal)
Loop
0 = Loop Disabled
1 = Loop Enabled
0 = DTR Output High (inactive)
1 = DTR Output Low (active)
0 = RTS Output High (inactive)
1 = RTS Output Low (active)
No Effect on External Operation
0 = External Interrupt Disabled
1 = External Interrupt Enabled
Bits Are Cleared
Figure 20. Modem Control Register Contents
modem status register (MSR)
The MSR provides the CPU with status of the modem input lines from the modem or peripheral devices. The
MSR allows the CPU to read the serial channel modem signal inputs. This is done by accessing the data bus
interface of the ACE in addition to the current status of four bits of the MSR. These four bits indicate whether
the modem inputs have changed since the last reading of the MSR. The delta status bits are set when a control
input from the modem changes state and are cleared when the CPU reads the MSR.
The modem input lines are CTS, DSR, RI, and DCD. MSR4 – MSR7 are status indicators of these lines. A set
status bit indicates that the input is low. A cleared status bit indicates that the input is high. When the modem
status interrupt in the interrupt enable register is enabled (IER3), an interrupt is generated whenever MSR0 –
MSR3 is set. The MSR is a priority-4 interrupt. The contents of the MSR are described in Table 11.
Bit 0: MSR0 is the delta clear-to-send (
CTS) bit.
CTS displays that the CTS input to the serial channel
has changed states since it was last read by the CPU.
Bit 1: MSR1 is the delta data set ready (
DSR) bit.
DSR indicates that the DSR input to the serial channel
has changed states since the last time it was read by the CPU.
Bit 2: MSR2 is the trailing edge of the ring indicator (TERI) bit. TERI indicates that the RI input to the serial
channel has changed states from low to high since the last time it was read by the CPU. High-to-low
transitions on RI do not activate TERI.
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參數(shù)描述
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