參數(shù)資料
型號(hào)： TL16C552AMFN
廠商： Texas Instruments, Inc.
英文描述： DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO
中文描述： 雙異步通信元帶有FIFO
文件頁數(shù)： 10/39頁
文件大?。?/td> 545K
代理商： TL16C552AMFN
TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
parallel port timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Note 16 and Figures 15, 16, and 17)
MIN
MAX
UNIT
μ
s
μ
s
μ
s
tsu7
th6
tw6
td10
td11
tw7
tw8
td12
td13
td14
td15
td16
NOTES: 16. These parameters are not production tested.
17. td13–td16 are all measured with a 15-pF load.
Setup time, data valid before STB
↓
Hold time, data valid after STB
↑
Pulse duration, STB
↓
Delay time, BUSY
↑
to ACK
↓
Delay time, BUSY
↓
to ACK
↓
Pulse duration, BUSY
↑
Pulse duration, ACK
↓
Delay time, BUSY
↑
after STB
↑
Delay time, INT2
↓
after ACK
↓
(see Note 17)
Delay time, INT2
↑
after ACK
↑
(see Note 17)
Delay time, INT2
↑
after ACK
↑
(see Note 17)
Delay time, INT2
↓
after IOR
↑
(see Note 17)
1
1
1
Defined by printer
Defined by printer
Defined by printer
Defined by printer
Defined by printer
22
ns
20
ns
24
ns
25
ns
PARAMETER MEASUREMENT INFORMATION
2 V
0.8 V
CLK (XTAL1)
tw1
tw2
fclock = 16 MHz MAX
2 V
0.8 V
Figure 1. CLK Voltage Waveform
Device Under Test
680
82 pF
(see Note A)
2.54 V
TL16C552A
NOTE A: This includes scope and jig capacitance.
Figure 2. Output Load Circuit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TL16C552AMHV 制造商:Texas Instruments 功能描述:UART 2-CH 16Byte FIFO 5V 68-Pin CFPAK Tube 制造商:Rochester Electronics LLC 功能描述:DUAL 550 UART WITH CENTRONIX PORT - Bulk
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