參數(shù)資料
型號(hào)： TL16C552AMFN
廠商： Texas Instruments, Inc.
英文描述： DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO
中文描述： 雙異步通信元帶有FIFO
文件頁(yè)數(shù)： 29/39頁(yè)
文件大?。?/td> 545K
代理商： TL16C552AMFN
TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
master reset (continued)
Table 10. RESET Effects on Registers and Signals
REGISTER/SIGNAL
RESET CONTROL
RESET
Interrupt enable register
Reset
All bits cleared (0–3 forced and 4–7 permanent)
Interrupt identification register
Reset
Bit 0 is set,
, , , ,
cleared.
,
y
Line control register
Reset
All bits are cleared.
Modem control register
Reset
All bits are cleared (5–7 permanently).
FIFO control register
Reset
All bits are cleared.
Line status register
Reset
All bits are cleared, except bits 5 and 6 are set.
Modem status register
Reset
Bits 0–3 are cleared, bits 4–7 input signal.
SOUT
Reset
High
Interrupt (RCVR errors)
Read LSR/Reset
Low
Interrupt (receiver data ready)
Read RBR/Reset
Low
Interrupt (THRE)
Read IIR/Write THR/Reset
Low
Interrupt (modem status changes)
Read MSR/Reset
Low
OUT2
Reset
High
RTS
Reset
High
DTR
Reset
High
OUT1
Reset
High
modem control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 20. MCR can be written to
and read from. The RTS and DTR outputs are directly controlled by their control bits in this register. A high input
asserts a low signal (active) at the output terminals. The MCR bits are defined in the following bulleted list.
Bit 0: When MCR0 is set, the DTR output is forced low. When MCR0 is cleared, the DTR output is forced
high. The DTR output of the serial channel can be input into an inverting line driver in order to obtain the
proper polarity input at the modem or data set.
Bit 1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced
high. The RTS output of the serial channel can be input into an inverting line driver to obtain the proper
polarity input at the modem or data set.
Bit 2: MCR2 has no effect on operation.
Bit 3: When MCR3 is set, the external serial channel interrupt is enabled.
Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,
SOUT is set to the marking (high) state and the SIN is disconnected. The output of the transmitter shift
register is looped back into the receiver shift register input. The four modem control inputs (CTS, DSR, DCD,
and RI) are disconnected. The modem control outputs (DTR, RTS, OUT1, and OUT2) are internally
connected to the four modem control inputs. The modem control output terminals are forced to their inactive
(high) state on the TL16C552A. In the diagnostic mode, data transmitted is immediately received. This
allows the processor to verify the transmit and receive data paths of the selected serial channel. Interrupt
control is fully operational; however, interrupts are generated by controlling the lower four MCR bits
internally. Interrupts are not generated by activity on the external terminals represented by those four bits.
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參數(shù)描述
TL16C552AMHV 制造商:Texas Instruments 功能描述:UART 2-CH 16Byte FIFO 5V 68-Pin CFPAK Tube 制造商:Rochester Electronics LLC 功能描述:DUAL 550 UART WITH CENTRONIX PORT - Bulk
TL16C552AMHVB 制造商:Texas Instruments 功能描述:5962-9755001QXA DUAL 550 UART 制造商:Texas Instruments 功能描述:UART 2-CH 16Byte FIFO 5V 68-Pin CFPAK Tube
TL16C552AMPN 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO
TL16C552APN 功能描述:UART 接口集成電路 Dual UART w/16-Byte FIFOs & Para Port RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C552APNG4 功能描述:UART 接口集成電路 Dual UART w/ 16-Byte FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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