參數(shù)資料
型號(hào)： TL16C552AMFN
廠商： Texas Instruments, Inc.
英文描述： DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO
中文描述： 雙異步通信元帶有FIFO
文件頁(yè)數(shù)： 18/39頁(yè)
文件大小： 545K
代理商： TL16C552AMFN
TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic
abbreviations for the internal registers are shown in Table 1.
Table 1. Internal Register Mnemonic Abbreviations
CONTROL
MNEMONIC
STATUS
MNEMONIC
DATA
MNEMONIC
Line control register
LCR
Line status register
LSR
Receiver buffer register
RBR
FIFO control register
FCR
Modem status register
MSR
Transmitter holding register
THR
Modem control register
MCR
Divisor latch LSB
DLL
Divisor latch MSB
DLM
Interrupt enable register
IER
The address, read, and write inputs are used with the divisor latch access bit (DLAB) in the line control register (bit 7)
to select the register to be written to or read from (see Table 2). Individual bits within the registers are referred to by
the register mnemonic and the bit number in parenthesis. As an example, LCR7 refers to line control register bit 7.
The transmitter holding register and receiver buffer register are data registers that hold from five to eight bits of data.
If fewer than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always the first
serial data bit received and transmitted. The ACE data registers are double buffered (TL16C450 mode) or FIFO
buffered (FIFO mode) so that read and write operations can be performed when the ACE is performing the
parallel-to-serial or serial-to-parallel conversion.
Table 2. Register Selection
DLAB
A2
A1
A0
MNEMONIC
REGISTER
L
L
L
L
RBR
Receiver buffer register (read only)
L
L
L
L
THR
Transmitter holding register (write only)
L
L
L
H
IER
Interrupt enable register
X
L
H
L
IIR
Interrupt identification register (read only)
X
L
H
L
FCR
FIFO control register (write only)
X
L
H
H
LCR
Line control register
X
H
L
L
MCR
Modem control register
X
H
L
H
LSR
Line status register
X
H
H
L
MSR
Modem status register
X
H
H
H
SCR
Scratch pad register
H
L
L
L
DLL
LSB divisor latch
H
L
L
H
DLM
MSB divisor latch
The serial channel is accessed when either CS0 or CS1 is low.
X = irrelevant, L = low level, H = high level
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