參數(shù)資料
型號: TL16C552AMFN
廠商: Texas Instruments, Inc.
英文描述: DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO
中文描述: 雙異步通信元帶有FIFO
文件頁數(shù): 28/39頁
文件大?。?/td> 545K
代理商: TL16C552AMFN
TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
line status register (LSR) (continued)
NOTE:
The LSR may be written to. However, this function is intended only for factory test. It should be
considered as read only by applications software.
Table 9. Line Status Register Bits
LSR BITS
1
0
LSR0 data ready (DR)
Ready
Not ready
LSR1 overrun error (OE)
Error
No error
LSR2 parity error (PE)
Error
No error
LSR3 framing error (FE)
Error
No error
LSR4 break interrupt (BI)
Break
No break
LSR5 transmitter holding register empty (THRE)
Empty
Not empty
LSR6 transmitter empty (TEMT)
Empty
Not empty
LSR7 receiver FIFO error
Error in FIFO
No error in FIFO
master reset
After power up, the ACE RESET input should be held low for one microsecond to reset the ACE circuits to an
idle mode until initialization. A low on RESET causes the following:
It initializes the transmitter and receiver clock counters.
It clears the LSR except for transmitter shift register empty (TEMT) and transmit holding register empty
(THRE), which are set. The MCR is also cleared. All of the discrete lines, memory elements, and
miscellaneous logic associated with these register bits are also cleared or turned off. The LCR, divisor
latches, receiver buffer register, and transmitter holding buffer register are not affected.
Following the removal of the reset condition (RESET high), the ACE remains in idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bit in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the effect of a reset on the ACE is given in Table 10.
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