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參數(shù)資料
| 型號： | TDA1373H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | General Digital Input GDIN |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-319-1, QFP-64 |
| 文件頁數(shù)： | 26/40頁 |
| 文件大?。?/td> | 308K |
| 代理商： | TDA1373H |
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1996 Jul 17
26
Philips Semiconductors
Product specification
General Digital Input (GDIN)
TDA1373H
Data path switching
All data path switches are freely controllable, although not all combinations make sense in the different operating modes.
Table 11 shows the preferred settings of the CMD3 control register.
Table 11
Preferred settings of the CMD3 control register
Notes
1.
2.
Level 0 or 1 indicates to set the flag in this position. A = application dependent.
When the output of the internal ADIC is fed directly to DO1 or FO, the serial output format is I
2
S, the word select
jitters (by one 384f
so
clock cycle) and the number of bit clocks per word select is not fixed.
S
TAND
-
ALONE CONTROL
When pin SA is HIGH, the GDIN operates under stand-alone control. Some basic settings can be controlled in this event
by changing the level at the control pins. Table 12 shows which command bits are pin-controllable during stand-alone
operation. The command bits which are not pin-controllable are automatically set to their appropriate value in accordance
with the selected mode (SRC or AD/DA). All control bits not shown get the value 0 in the event of stand-alone control.
Table 12
Command registers
Notes
1.
2.
When the device operates in stand-alone control, only the SRC mode and AD/DA mode are available.
This means that all 3-state outputs are permanently enabled during stand-alone operation.
REGISTER
BIT
FLAG
DATA PATH SWITCH
SRC
(1)
SLAVE
(1)
AD/DA
(1)
CMD3 (02H)
data path
7
6
5
4
3
2
1
0
DSO
FOS
DI2
DNI
AOS
DO2
DO1 output selector; note 2
reserved
FO output selector; note 2
FIFO input selector
input selector 128
×
filter
reserved
AOL and AOR output selector
DO2 output selector
0
A
A
0
A
0
A
A
A
1
A
A
A
A
A
1
A
A
REGISTER
FLAG
PIN
DESCRIPTION
EXPLANATION
CMD1 (00H) ADIC
control
CMD2 (01H) loop
and mode control
DI11
FSL
ADIC input selector
0 = DI1S;
1 = DI1O
0 = SRC mode;
1 = AD/DA mode
RTR is always 1 in stand-alone
mode
0 = FOW, FOD and FOC;
1 = DI2W, DI2D and DI2C
SRC mode = 0: variable hold;
AD/DA mode = 1: AIL/AIR
0 = 20 bit; 1 = 16 bit INS
0 = OFF; 1 = ON
gain = 01111111 =
×
0.992
MS0
DI1D
mode selector; note 1
RTR
enable 3-state outputs; note 2
CMD3 (02H)
data path
DI2
DA
FIFO input selector
DNI
input selector 128
×
filter
CMD4 (03H)
control
QU0/QU1
NSD
GAIN
CL
LD
in-band noise shaper
dither Bitstream digital
gain of the FIFO/GAIN block
CMD6 (05H)
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