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參數(shù)資料
| 型號： | TDA1373H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | General Digital Input GDIN |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-319-1, QFP-64 |
| 文件頁數(shù)： | 25/40頁 |
| 文件大小： | 308K |
| 代理商： | TDA1373H |
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1996 Jul 17
25
Philips Semiconductors
Product specification
General Digital Input (GDIN)
TDA1373H
Notes
1.
2.
3.
In the SLAVE-VCXO mode, the PLL should be fixed in state 2 until locked.
A mode change will always invoke a restart of the GDIN.
At power-on the DO1 and FO outputs are ‘3-state’ to avoid I
2
S bus conflicts. This bit overrides the serial I/O
control bits.
A MRS or hardware reset clears all command registers, also the MRS flag itself.
See Section “Data path switching” for possible settings of the data path switches in the different modes.
Set all reserved flags to 0.
Setting MMU starts a soft-mute from current gain value to 0 by
1
128
per input sample. Clearing MMU starts the
inverse process from 0 to current gain value.
To prevent idle patterns in the audio band, it is strongly advised to add out-of-band dither by setting control bit NSD.
Set this bit for 32 kHz input sources.
10. Use ‘01111111’ for normal operation to avoid pass band ripple clipping.
4.
5.
6.
7.
8.
9.
CMD4 (03H)
control
7
6
5
reserved
reserved
soft mute function; note 7
in-band noise shaper
0 = OFF; 1 = ON
00 = 16-bit; 01 = 20-bit;
10 = 16-bit INS; 11 = 18-bit INS
0 = OFF; 1 = ON
MMU
4 and 3
QU1 and QU0
2
NSD
dither Bitstream digital filter;
note 8
symmetrical Bitstream output
stop band suppression 64
×
filter;
note 9
serial format DI2 input
1
0
DLO
SSP
0 = OFF; 1 = ON
0 = 70 dB; 1 = 50 dB
CMD5 (04H)
input/output
formats
7 and 6
DI22 and DI21
00 = I
2
S; 01 = Japanese 16-bit;
10 = Japanese 18-bit;
11 = Japanese 20-bit
00 = I
2
S; 01 = Japanese 16-bit;
10 = Japanese 18-bit;
11 = reserved
00 = I
2
S; 01 = Japanese 16-bit;
10 = Japanese 18-bit;
11 = 3-stated
0 = master; 1 = slave
0 = I
2
S; 1 = 3-stated
some examples:
11111111 =
×
2 (maximum)
10000000 =
×
1
01111111 =
×
0.992
00000001 =
×
0.0078
5 and 4
DO22 and
DO21
serial format DO2 output
3 and 2
DO12 and
DO11
serial format DO1 output
1
0
7
6
5
4
3
2
1
0
DO1M
FOT
GAIN7
GAIN6
GAIN5
GAIN4
GAIN3
GAIN2
GAIN1
GAIN0
DO1 master/slave selector
FO output 3-state selector
GAIN7 to GAIN0: gain of the
GCM block
(10)
; maximum = 2;
step =
1
128
CMD6 (05H)
REGISTER
BIT
FLAG
DESCRIPTION
EXPLANATION
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