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參數(shù)資料
| 型號： | TDA1373H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | General Digital Input GDIN |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-319-1, QFP-64 |
| 文件頁數(shù)： | 13/40頁 |
| 文件大?。?/td> | 308K |
| 代理商： | TDA1373H |
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1996 Jul 17
13
Philips Semiconductors
Product specification
General Digital Input (GDIN)
TDA1373H
Description of functional blocks
IEC 958
AUDIO DIGITAL INPUT CIRCUIT
The TDA1373H has three IEC 958 inputs:
1.
DI1S.
2.
DI1O.
3.
DI1D.
DI1S accepts IEC 958 line signals (minimum 200 mV
peak-to-peak value and maximum 5 V peak-to-peak
value), DI1O and DI1D accept only CMOS level signals.
The input sample rate range that can be handled depends
on the output sample frequency (f
so
) of the device.
The maximum useful word length of the incoming samples
is 20 bits.
The internal ADIC retrieves the stereo audio samples, the
V, U, C and P data bits, the ADIC word clock and the bit
clock from the selected IEC 958 input signal. The digital
ADIC locks in less than 1 ms for a 44.1 kHz input signal.
During this lock-in time the word clock is stopped and the
audio bits are muted.
The validity flag (VA), pre-emphasis flag and pin (EM), lock
flag (LCK) and lock pin (LOCK) are available to check the
status of the ADIC. This validity flag is an OR-ing of the
incoming validity (V) bit and the own error detection of the
ADIC. The actions which take place in case of detected
errors are listed in Table 2.
Table 2
Error concealment in the IEC 958 decoder
ERROR
ACTION DATA
ACTION WORD CLOCK
Validity (V-bit) error
Parity (P-bit) error
Number of data bits
≠
32
Missing pre-amble(s)
Extra pre-amble(s)
More than 4 pre-ambles missing or extra mute output; restart
pass sample
repeat last correct sample
no action
stop ADIC word clock
S
ERIAL DIGITAL INPUTS
DI2W, DI2D
AND
DI2C
The serial digital input DI2 can be used as standard input
instead of the DI1 IEC 958 input or can be used together
with the FO-output to switch a DSP IC in the input data
path. A third possibility is to use DI2 as direct input to the
GDIN Bitstream digital filter. In that case the DI2 input
signal should be 4
×
oversampled externally. The serial
formats supported are shown in Fig.7 and Table 3.
Table 3
Serial input and output formats (see note 1)
Note
1.
S = slave; M = master.
INPUT
OUTPUT
f
WS
f
BCK
I
2
S
JAPANES
E 16-BIT
JAPANESE
18-BIT
JAPANESE
20-BIT
3-STATE
CONTROL BITS
DI2
f
si
4f
so
f
so
≤
128f
si
192f
so
48f
so
≤
128f
so
192f
so
64f
so
S
M
M
S
M
M
S
S
M
M
S
S
M
M
S
S
no
no
DI2, DI21 and DI22
DI2
DO1
yes
DO1S, DO11 and DO12
DO2
FO
4f
so
f
si
no
yes
DO2, DO21 and DO22
FO and FO1
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